Semiconductor Package Edge Center Pad Wire Bonding Layout

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Solution Overview

Problem

Current semiconductor packages face challenges in achieving higher performance and reliability due to limitations in chip mounting area and wire bonding configurations, which can lead to short circuits and reduced efficiency.

Innovation Solution

The semiconductor package design includes a substrate with bonding pads and controllers positioned between chip structures, utilizing edge and center pads connected by bonding wire structures to minimize chip mounting area and prevent short circuits, while also using encapsulants to protect against environmental factors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If chip mounting area is reduced to increase device density, then productivity and device capacity are improved, but wire bonding configurations may lead to short circuits and reduced reliability

Engineering Contradiction:
Improvedevice densityVSAvoidshort circuit prevention
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The bonding pads are segmented into edge pads located at peripheral regions and center pads located at central regions of the substrate. This spatial segmentation allows wire bonds to be routed through different zones, reducing the probability of short circuits while maintaining high device density through optimized space utilization.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Controllers are positioned as intermediary elements between chip structures, with their edge pads and center pads providing intermediate connection points. This intermediary arrangement enables wire bonds to pass through controller regions without directly connecting adjacent chip structures, thereby preventing short circuits while maintaining compact mounting.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Speed

If controllers are positioned between chip structures to improve communication efficiency, then loading speed is improved, but chip mounting area increases

Engineering Contradiction:
Improveloading speedVSAvoidchip mounting area
Core Design Contradiction:
SpeedVSArea of stationary object

Solution Approach 1:

The layout transitions from a one-dimensional linear arrangement to a two-dimensional planar configuration where controllers are positioned between chip structures and bonding pads are distributed at both edge and center regions. This dimensional expansion enables efficient communication pathways without proportionally increasing the overall mounting area.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

Different regions of the substrate are assigned different functions: edge regions contain edge pads for specific connections, center regions contain center pads for other connections, and intermediate regions contain controllers. This local differentiation optimizes communication efficiency in critical paths while minimizing overall area consumption.

Inventive Principle:
Principle #3Local quality

3Reliability

If edge pads and center pads are used to optimize wire bonding paths, then short circuit prevention is improved, but device complexity increases

Engineering Contradiction:
Improveshort circuit preventionVSAvoidbonding pad configuration
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

Both edge pads and center pads serve the same fundamental function of electrical connection, but are positioned differently to achieve short circuit prevention. This functional universality simplifies the design rule set compared to having entirely different connection mechanisms for different regions, while still providing the reliability benefits of spatially distributed bonding paths.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS20230343746A1Semiconductor package
Publication Date: 2023.10.26 SAMSUNG ELECTRONICS CO LTD
  • US20230343746A1 patent drawing
  • US20230343746A1 patent drawing
  • US20230343746A1 patent drawing

AI summary

A semiconductor package includes a substrate, a first chip structure disposed on the substrate, a second chip structure disposed on the substrate, at least one controller disposed between the first chip structure and the second chip structure, the at least one controller including edge pads disposed on edges opposing each other in a first direction, and center pads disposed between the edge pads, and bonding wire structures. The substrate includes first bonding pads arranged in a second direction, perpendicular to the first direction, and second bonding pads arranged in the second direction in at least one of a space between the first bonding pads and the first chip structure and a space between the first bonding pads and the second chip structure. The bonding wire structures include a first bonding wire structure connecting the edge pads to the first bonding pads, and a second bonding wire structure connecting the center pads to the second bonding pads.