Semiconductor Package Edge Recess Structure for Molding Planarity
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Solution Overview
Problem
The increasing size of semiconductor chips and decreasing thickness of semiconductor packages due to slimming electronic devices lead to reliability issues, particularly in fan-out panel level packages where the molding layer thickness in the edge region increases, compromising package reliability.
Innovation Solution
A semiconductor package design that includes etching the upper portion of the insulating layer in the edge region to form recesses, which are then filled by a molding layer, ensuring a planar upper surface and preventing protrusion, thereby maintaining package reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the size of semiconductor chip increases to implement high-performance elements, then the performance is improved, but the size of semiconductor package increases, conflicting with slimming trend
Solution Approach 1:
The patent addresses the size conflict by utilizing vertical dimensionality changes through the recess formation. By creating a localized depression in the edge region, the solution allows the molding layer to fill this recess and maintain a planar upper surface, effectively managing the vertical profile of the package. This enables larger chips to be accommodated while controlling the overall package thickness through strategic use of vertical space management in the edge regions.
Data Source
AI summary
A semiconductor package including a first redistribution structure including a first redistribution layer disposed therein, a first semiconductor chip disposed on the first redistribution structure, an insulating layer surrounding a sidewall of the first semiconductor chip, the insulating layer spaced apart from the first semiconductor chip in a horizontal direction, a first connection structure extending through the insulating layer in a vertical direction, connected to the first redistribution structure, and includes a first via disposed inside the insulating layer. A second connection structure disposed between the first semiconductor chip and the first connection structure, extends through the insulating layer in the vertical direction, connected to the first redistribution structure, and includes a second via disposed inside the insulating layer. A molding layer covering the first semiconductor chip, a sidewall and an upper surface of the insulating layer. At least a portion of the molding layer disposed between the first and second vias.