Semiconductor Package Edge-Mounted Terminals for Reduced Footprint
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Solution Overview
Problem
Conventional high power semiconductor packages require a large PCB footprint due to the source-down or drain-down configuration, leading to increased costs and shared thermal paths, which limits efficient heat dissipation and electrical connectivity.
Innovation Solution
A semiconductor package design where the semiconductor die is mounted with its edge facing the substrate, utilizing terminals on both sides with a mold compound that leaves part of the terminals uncovered to enhance heat dissipation and reduce footprint, and optionally incorporating cooling structures or protrusions for improved thermal management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional source-down or drain-down configuration is used, then electrical connectivity is achieved, but PCB footprint area increases
Solution Approach 1:
The patent transitions from a conventional planar mounting configuration to a three-dimensional package structure where the semiconductor die is mounted vertically on the PCB with its side surface facing the substrate. This dimensional change allows electrical connections to be made through the thickness of the package rather than requiring large planar footprints, thereby reducing the PCB area occupation while maintaining electrical connectivity.
Solution Approach 2:
Instead of mounting the semiconductor die with its main surface facing the PCB (conventional approach), the patent inverts the mounting orientation so that the side surface of the die faces the PCB. This inversion fundamentally changes the connection geometry and enables compact footprint design.
2Reliability
If conventional PCB configuration is used, then electrical path is provided, but thermal path sharing increases
Solution Approach 1:
The patent separates the electrical connection function from the thermal management function by using distinct structural elements. The metal clips or bonding wires provide electrical connectivity, while the protrusion extending from the mold compound provides dedicated thermal conduction path to the heat sink, preventing thermal path sharing with other PCB components.
Solution Approach 2:
The patent introduces an intermediary thermal conduction structure (protrusion extending from mold compound) that mediates between the semiconductor die and the heat sink. This intermediary element provides a dedicated thermal pathway that is independent of the PCB thermal paths, allowing efficient heat dissipation without sharing thermal paths with other components.
3Reliability
If metal clips or bonding wires are used for connection, then electrical connectivity is achieved, but package complexity increases
Solution Approach 1:
The patent merges multiple functions into integrated structures. The metal clips serve both as mechanical support and electrical connection elements, while the protrusion structure simultaneously provides mechanical alignment, thermal conduction, and electrical isolation functions, thereby reducing overall package complexity despite maintaining robust electrical connectivity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration results in a smaller package footprint, improved heat dissipation through the terminals, and efficient electrical connectivity, reducing costs and thermal path sharing on the PCB.
Implementation Method 1
a mold compound enclosing at least part of the semiconductor die and the first and second terminals
Implementation Method 2
improved heat dissipation through the terminals
Implementation Method 3
Cooling structures are patterned into the at least partly uncovered side of at least one of the first and second terminals for increasing the surface area of that side
Data Source
AI summary
A semiconductor assembly includes a substrate with electrically conductive regions and a semiconductor package. The semiconductor package includes a semiconductor die, first and second terminals, and a mold compound. The die has opposing first and second main surfaces, an edge disposed perpendicular to the first and second main surfaces, a first electrode at the first main surface, and a second electrode at the second main surface. The first terminal is attached to the first electrode. The second terminal is attached to the second electrode. The mold compound encloses at least part of the die and the first and second terminals so that each of the terminals has a side parallel with and facing away from the die that remains at least partly uncovered by the mold compound. The first and second terminals of the semiconductor package are connected to different ones of the electrically conductive regions of the substrate.