Semiconductor Package With Embedded Bridge Chip
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Solution Overview
Problem
Current semiconductor packaging technologies face challenges in increasing chip capacity within limited space, requiring advanced techniques like multi-chip stacking, while also dealing with issues such as high manufacturing costs and warpage during the mounting of fine structure solder bumps on printed circuit boards.
Innovation Solution
A semiconductor package design that includes a substrate, a rewiring layer with a concave portion, and a second semiconductor chip acting as a bridge layer to electrically connect multiple chip stack structures, minimizing internal wirings and using a fine line structure to enhance connectivity and reduce warpage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-chip stacking technology is used to increase chip capacity in limited space, then chip capacity is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent introduces a rewiring layer as an intermediary component between the substrate and multiple semiconductor chips. This rewiring layer integrates routing functions that would otherwise require complex internal wirings in each chip, thereby enabling multi-chip stacking to increase capacity while managing manufacturing complexity through a dedicated intermediary structure.
Solution Approach 2:
The patent transitions from planar chip arrangement to three-dimensional multi-chip stacking configuration. By utilizing vertical stacking along the Z-axis in addition to horizontal arrangement, the system achieves higher chip capacity within limited footprint area, resolving the contradiction between capacity and space constraints.
2Reliability
If fine line structure is used to enhance connectivity, then electrical connectivity is improved, but warpage during mounting increases
Solution Approach 1:
The patent modifies the physical and material parameters of the rewiring layer, including its thickness, material composition, and structural configuration. By optimizing these parameters, the rewiring layer achieves appropriate flexibility to accommodate thermal expansion and contraction during mounting processes, thereby reducing warpage while maintaining fine line electrical connectivity for reliable signal transmission.
Data Source
AI summary
A semiconductor package includes a substrate, a rewiring layer, a plurality of semiconductor chip stack structures, and a second semiconductor chip. The rewiring layer is disposed on an upper surface of the substrate. The rewiring layer includes a concave portion. The semiconductor chip stack structures include a plurality of first semiconductor chips. The first semiconductor chips are disposed on the rewiring layer. The first semiconductor chips are spaced apart from each other in a horizontal direction. The second semiconductor chip is disposed within the concave portion. The second semiconductor chip is configured to electrically connect each of the plurality of semiconductor chip stack structures to each other.