Semiconductor Package Embedded Die Stud Bump Interconnections

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Solution Overview

Problem

Conventional semiconductor packaging technologies face limitations in z-axis integration due to limited pitch between vertical connections, height variations, noncoplanar circuitry traces, and increased footprint, leading to inefficient physical and electrical contact.

Innovation Solution

The use of stud bump interconnections on a semiconductor package with a dielectric encapsulating layer and a circuitry layer, allowing for fine pitch and coplanar contact sites, enabling robust connections and miniaturization by forming vertical interconnections between the die and substrate without the need for wire bonds.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional laser drilling or other known techniques are used for forming holes in the encapsulating layer, then vertical connections can be established, but the pitch between vertical connections is limited to about 125 microns

Engineering Contradiction:

Improvepitch between vertical connectionsVSAvoidintegration density along z-axis

Core Design Contradiction:

Manufacturing precisionVSProductivity

Solution Approach 1:

The patent changes the fundamental parameter of how vertical connections are formed by replacing laser drilling with stud bump formation. This enables pitch reduction from 125 microns to 80 microns or less, directly resolving the contradiction between manufacturing precision and integration density.

Inventive Principle:

Principle #35Parameter changes

2Manufacturing precision

If conventional drilling processes are used to form vertical connections, then connections can be established, but height variations among vertical connections occur which produce noncoplanar traces in the circuitry layer

Engineering Contradiction:

Improvecoplanarity of circuitry layer tracesVSAvoidphysical and electrical contact of mounted component

Core Design Contradiction:

Manufacturing precisionVSReliability

Solution Approach 1:

The patent replaces the mechanical drilling process with a metallurgical bonding process (stud bump formation). This substitution eliminates the height variation problem inherent in drilling, ensuring coplanar traces and reliable component contact.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

3Reliability

If holes in the encapsulating layer are plated several times to form solid vertical interconnections, then reliable electrical connections can be achieved, but manufacturing complexity and cost increase

Engineering Contradiction:

Improvesolid vertical interconnectionsVSAvoidnumber of plating steps

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts and eliminates the multiple plating steps from the manufacturing process by using stud bump formation that creates solid vertical interconnections in a single step, reducing complexity while maintaining reliability.

Inventive Principle:

Principle #2Taking out (Extraction)

4Reliability

If traces in the circuitry layer are flared or enlarged to capture upper ends of vertical connections, then electrical connections can be established, but trace density decreases

Engineering Contradiction:

Improveelectrical connection between traces and vertical connectionsVSAvoidtrace density in circuitry layer

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent changes the geometry parameter of the vertical connections by using stud bumps with controlled dimensions that do not require trace flaring. This maintains high trace density while ensuring reliable electrical connections.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS9385074B2Semiconductor package with embedded die

Publication Date: 2016.07.05 STATS CHIPPAC LTD

AI summary

A semiconductor package having an embedded die and solid vertical interconnections, such as stud bump interconnections, for increased integration in the direction of the z-axis (i.e., in a direction normal to the circuit side of the die). The semiconductor package can include a die mounted in a face-up configuration (similar to a wire bond package) or in a face-down or flip chip configuration.