Semiconductor Package with Embedded Passive Components for Lower Profile
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Solution Overview
Problem
Existing semiconductor packages face challenges in miniaturization due to the height of passive components, which increases the overall package size and hinders the integration of multiple chips in a compact form factor.
Innovation Solution
A semiconductor package design that incorporates a lower redistribution structure with a cavity for passive components, filled with an insulation filler, and a semiconductor chip connected to both the redistribution pattern and passive component, allowing for a reduced external connection bump height and enabling miniaturization through the burial of passive components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If passive components are placed on the surface of the package substrate, then they are easily accessible and simple to manufacture, but the overall package height increases
Solution Approach 1:
The passive components are embedded within cavities formed in the package substrate, nesting them inside the substrate volume rather than placing them on the surface. This nesting approach reduces the external package height while maintaining manufacturing simplicity through standardized cavity formation processes
Solution Approach 2:
The passive components are transitioned from a two-dimensional surface placement to a three-dimensional embedded configuration within the substrate thickness. This dimensional change allows the components to occupy internal space, reducing the external footprint and package height
2Volume of moving object
If the package size is reduced for miniaturization, then portability is improved, but the integration of multiple chips becomes difficult
Solution Approach 1:
The package substrate is segmented into multiple regions with different cavity depths and configurations, allowing different types of chips and passive components to be integrated in specific zones. This segmentation enables multi-chip integration while maintaining a compact overall package volume
Solution Approach 2:
Different regions of the package substrate are designed with locally optimized properties, including varying cavity depths, wall thicknesses, and material compositions. This local quality variation allows specific areas to accommodate different chip types and connection requirements, enhancing integration capability within a reduced package volume
3Length of stationary object
If the external connection bump height is reduced, then the package profile is minimized, but the electrical connection reliability may be compromised
Solution Approach 1:
The cavity structures are pre-formed in the package substrate before mounting the chips and forming the connection bumps. This preliminary action creates prepared receptacles that guide and support the connection bumps, ensuring proper alignment and mechanical support even when the bumps have reduced height
Solution Approach 2:
The cavity walls and insulation fillers act as intermediary structures between the connection bumps and the underlying trace patterns. These intermediaries provide mechanical support, electrical isolation, and stress distribution, maintaining connection reliability despite reduced bump heights
Data Source
AI summary
A semiconductor package includes: a lower redistribution structure including a lower redistribution insulation layer, a bump pad in the lower redistribution insulation layer, and a lower redistribution pattern electrically connected to the bump pad, wherein the lower redistribution insulation layer includes: one or more sidewalls at least partially defining a cavity extending from a bottom surface of the lower redistribution insulation layer to an upper surface of the lower redistribution insulation layer; a passive component in the cavity of the lower redistribution insulation layer; an insulation filler in the cavity of the lower redistribution insulation layer, the insulation filler covering sidewalls of the passive component; a first semiconductor chip on the lower redistribution structure, the first semiconductor chip electrically connected to both the lower redistribution pattern and the passive component; and an external connection bump connected to the bump pad via a pad opening of the lower redistribution insulation layer.