Semiconductor Package Layout With Embedded Trace Substrate
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Solution Overview
Problem
Conventional semiconductor package technologies face challenges in achieving high integration density and performance due to long electrical paths and increased turnaround time in forming metal posts, which can lead to yield degradation.
Innovation Solution
The implementation of a package on package technology using wire bonding to electrically connect upper semiconductor dies to the front side redistribution layer structure and utilizing an embedded trace substrate instead of conductive posts to connect the front and back side redistribution layers, reducing the electrical path length and metal post usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conductive posts are used to connect front side redistribution layer structure and back side redistribution layer structure, then electrical connection is achieved, but electrical path length increases and turnaround time increases
Solution Approach 1:
The patent transitions from vertical through-substrate connections (conductive posts) to surface-level connections using embedded trace substrate technology. The trace substrate is embedded in the molding compound, allowing electrical connections to be made at a different spatial dimension (surface level rather than through the substrate), thereby reducing the electrical path length while maintaining connection reliability.
2Reliability
If metal posts are formed using exposure, development, etching, and deposition processes, then electrical connection is achieved, but turnaround time increases and yield degradation risk occurs
Solution Approach 1:
The patent extracts the complex multi-step metal post formation process (exposure, development, etching, deposition) and replaces it with a simplified embedded trace substrate approach. The trace substrate is pre-fabricated with conductive traces, eliminating the need for repeated semiconductor fabrication processes, thereby reducing turnaround time and minimizing yield degradation risks while maintaining electrical connection reliability.
3Reliability
If multiple exposure, development, etching, and deposition processes are repeated to form metal posts, then electrical connection is achieved, but manufacturing complexity increases
Solution Approach 1:
The patent applies preliminary action by pre-fabricating the conductive traces on the trace substrate before embedding it in the molding compound. The trace substrate is manufactured with all necessary conductive patterns in advance, eliminating the need to repeat exposure, development, etching, and deposition processes during package assembly. This preliminary preparation simplifies the overall manufacturing process while ensuring reliable electrical connections.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of high-performance semiconductor packages with reduced electrical paths, shorter turnaround times, and improved yield by eliminating the need for lengthy metal post formation processes.
Implementation Method 1
an upper semiconductor die among semiconductor dies stacked on a front side redistribution layer structure and the front side redistribution layer structure may be electrically connected through wire bonding
Data Source
AI summary
An embodiment of the present invention provides a semiconductor package including: a first redistribution layer structure; a semiconductor stack structure on the first redistribution layer structure, the semiconductor stack structure including a first semiconductor die and a second semiconductor die on the first semiconductor die; a plurality of wires configured to electrically connect the second semiconductor die to the first redistribution layer structure; a substrate on the first redistribution layer structure and around the semiconductor stack structure; a molding material configured to mold the semiconductor stack structure and the wires on the first redistribution layer structure; and forming a second redistribution layer structure on the molding material.