Semiconductor Package EMI Shielding via Segmented Connection Structure

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing semiconductor packages face defects and compromised electromagnetic interference (EMI) shielding performance due to the deposition of metal layers on lower surfaces during the sputtering process, leading to issues like appearance and electrical shorts.

Innovation Solution

A semiconductor package design with a multi-stage connection structure and EMI shielding layer that does not extend to the lower surface, featuring first and second regions with different widths, allowing for controlled deposition of the metal layer to prevent defects and enhance shielding.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Object-affected harmful factors

If a metal layer is formed by sputtering to provide EMI shielding, then electromagnetic shielding performance is improved, but metal layer deposits on the lower surface causing appearance defects, solder balls, and electrical shorts

Engineering Contradiction:
ImproveEMI shielding performanceVSAvoiddefect occurrence
Core Design Contradiction:
Object-affected harmful factorsVSReliability

Solution Approach 1:

The connection structure is divided into a first region and a second region with different widths, creating distinct zones that control where the metal layer deposits. This segmentation allows the EMI shielding layer to be formed only on the first region while preventing deposition on the second region and lower surface, thus resolving the contradiction between achieving shielding performance and avoiding defects

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The connection structure has different widths at different locations (first region vs. second region), creating local structural variations. This local quality difference ensures that the metal layer deposits only on the wider first region where EMI shielding is needed, while the narrower second region remains free of metal deposition, preventing appearance defects and electrical shorts

Inventive Principle:
Principle #3Local quality

2Ease of manufacture

If the connection structure has uniform width to simplify manufacturing, then ease of manufacture is improved, but EMI shielding performance is compromised due to unwanted metal layer deposition

Engineering Contradiction:
Improvemanufacturing simplicityVSAvoidEMI shielding performance
Core Design Contradiction:
Ease of manufactureVSObject-affected harmful factors

Solution Approach 1:

The connection structure is segmented into regions with different widths, where the first region has a greater width than the second region. This segmentation is achieved through controlled sawing processes and allows selective formation of the EMI shielding layer on the first region, maintaining both manufacturing feasibility and effective EMI shielding performance

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Significantly reduces defect occurrence and improves EMI shielding performance by preventing metal layer deposition on the lower surface, thereby maintaining the integrity of the package and enhancing its electrical and thermal characteristics.

Implementation Method 1

When the deposition method such as sputtering is used, since a sputtering layer is formed even on a lower surface of the package according to formation of an EMI shielding layer

Methodology Applied
Scientific EffectSputtering: Sputtering

Data Source

PatentUS11652066B2Semiconductor package
Publication Date: 2023.05.16 SAMSUNG ELECTRONICS CO LTD
  • US11652066B2 patent drawing
  • US11652066B2 patent drawing
  • US11652066B2 patent drawing

AI summary

A method of manufacturing a semiconductor package includes forming an encapsulant covering at least a portion of each of an inactive surface and side surface of a semiconductor chip, the semiconductor chip having an active surface on which a connection pad is disposed and the inactive surface opposing the active surface; forming a connection structure having a first region and a second region sequentially disposed on the active surface of the semiconductor chip, and the connection structure including a plurality of redistribution layers electrically connected to the connection pad of the semiconductor chip and further including a ground pattern layer; and forming a metal layer disposed on an upper surface of the encapsulant, and extending from the upper surface of the encapsulant to a side surface of the first region of the connection structure.