Semiconductor Package Layout for Uniform Encapsulation at High Density

Solution Overview

Problem

Existing semiconductor packages face challenges in achieving uniform encapsulation and preventing delamination and void formation during the molding process due to uneven distribution of conductive pillars, which affects the integration density and reliability of the packages.

Innovation Solution

The introduction of dummy through-insulating vias (TIVs) and conductive pillars arranged in a specific configuration to enhance the flow uniformity of molding materials, providing stress relief and reducing delamination and voids, while maintaining a dense and reliable electrical connection network.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If conductive pillars are arranged densely to improve integration density, then integration density is improved, but uniformity of encapsulation and stress distribution deteriorates

Engineering Contradiction:

Improveintegration densityVSAvoiduniformity of encapsulation

Core Design Contradiction:

ProductivityVSManufacturing precision

Solution Approach 1:

The patent introduces dummy through-insulating vias (TIVs) as copies of the conductive pillar structure. These dummy TIVs replicate the physical presence and stress-distribution function of actual conductive pillars without providing electrical connectivity, thereby maintaining uniform encapsulation and stress distribution while allowing dense arrangement of functional conductive pillars to achieve high integration density.

Inventive Principle:

Principle #26Copying

Solution Approach 2:

The patent creates a homogeneous distribution of both functional and dummy through-insulating vias across the semiconductor package. This homogeneous arrangement ensures uniform encapsulation material flow and consistent stress distribution throughout the package, preventing delamination and void formation while supporting high integration density through proper spacing and distribution patterns.

Inventive Principle:

Principle #33Homogeneity

2Productivity

If conductive pillars are arranged densely to improve integration density, then integration density is improved, but delamination and void formation increase

Engineering Contradiction:

Improveintegration densityVSAvoiddelamination and void formation

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent introduces dummy through-insulating vias (TIVs) as copies of the conductive pillar structure. These dummy TIVs replicate the physical presence and stress-distribution function of actual conductive pillars without providing electrical connectivity, thereby maintaining uniform encapsulation and stress distribution while allowing dense arrangement of functional conductive pillars to achieve high integration density.

Inventive Principle:

Principle #26Copying

Solution Approach 2:

The patent creates a homogeneous distribution of both functional and dummy through-insulating vias across the semiconductor package. This homogeneous arrangement ensures uniform encapsulation material flow and consistent stress distribution throughout the package, preventing delamination and void formation while supporting high integration density through proper spacing and distribution patterns.

Inventive Principle:

Principle #33Homogeneity

3Manufacturing precision

If dummy TIVs are added to improve flow uniformity and reduce delamination, then encapsulation quality is improved, but device complexity increases

Engineering Contradiction:

Improveencapsulation qualityVSAvoidstructure complexity

Core Design Contradiction:

Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent introduces dummy through-insulating vias (TIVs) as copies of the conductive pillar structure. These dummy TIVs replicate the physical presence and stress-distribution function of actual conductive pillars without providing electrical connectivity, thereby maintaining uniform encapsulation and stress distribution while allowing dense arrangement of functional conductive pillars to achieve high integration density.

Inventive Principle:

Principle #26Copying

Solution Approach 2:

The dummy TIVs perform a temporary function during the encapsulation process by providing stress relief and uniform material flow paths. After serving this purpose, they remain as inactive structural elements that do not interfere with electrical functionality, effectively discarding electrical complexity while retaining structural benefits.

Inventive Principle:

Principle #34Discarding and recovering

Data Source

PatentUS12575465B2Semiconductor package and manufacturing method thereof

Publication Date: 2026.03.10 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A semiconductor package and a manufacturing method are provided. The semiconductor package includes a semiconductor die laterally covered by an insulating encapsulation, a first redistribution structure overlying the insulating encapsulation and a back surface of the semiconductor die, a second redistribution structure underlying the insulating encapsulation and an active surface of the semiconductor die opposite to the back surface, active through insulating vias (TIVs) penetrating through the insulating encapsulation, and dummy features. The semiconductor die is electrically coupled to the first redistribution structure through the second redistribution structure and the active TIVs. Each of the dummy features includes a dummy TIV laterally covered by the insulating encapsulation, the dummy TIVs are disposed along package edges in a top view, and the dummy features are electrically floating.