Semiconductor Package Error Correction via Dedicated Memory Controller
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Solution Overview
Problem
Current semiconductor package technologies face challenges in repairing defects detected at the package level, especially when multiple memory chips are mounted inside a single package, as wafer-level repairs are easier but not feasible post-packaging.
Innovation Solution
Incorporating a memory controller chip, multiple first memory chips for normal data storage, a second memory chip for error information storage, and an interface unit to manage data and error correction within the semiconductor package, utilizing error information like parity bits or ECC to correct data errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple memory chips are mounted inside a single package to increase capacity, then the storage capacity is improved, but the difficulty of detecting and measuring defects increases
Solution Approach 1:
The patent divides the error correction function into separate dedicated chips (first memory chips for normal data, second memory chip for error information) rather than attempting to monitor all chips simultaneously. This segmentation allows independent testing and error handling of each memory chip, making defect detection manageable even with multiple chips in the package.
Solution Approach 2:
The patent introduces a memory controller chip as an intermediary that coordinates error detection and correction across multiple memory chips. The controller manages the interface between chips and implements the error correction logic, simplifying the complexity of direct chip-to-chip monitoring and enabling scalable defect detection in multi-chip packages.
2Ease of repair
If wafer-level repair methods are used to replace defective cells, then the repair ease is improved, but the adaptability to package-level defects deteriorates
Solution Approach 1:
The patent performs error correction in advance by storing error information (parity bits or ECC data) in the second memory chip before data is needed. This preliminary error detection and correction capability is built into the package structure, allowing defects to be corrected at the package level without requiring wafer-level repair processes.
Solution Approach 2:
The patent creates a universal error correction system that can handle defects in any of the multiple memory chips through the same mechanism (second memory chip storing error information for all first memory chips). This multi-functional approach allows the same error correction infrastructure to serve all memory chips regardless of where defects occur, providing package-level repair capability that adapts to various defect scenarios.
Data Source
AI summary
A semiconductor package includes a memory controller chip, a plurality of first memory chips configured to store normal data, a second memory chip configured to store error information for correcting or detecting error of the normal data, and an interface unit configured to interface the memory controller chip, the plurality of first memory chips, and the second memory chip.