Semiconductor Package Contact Structure for Etched Non-Rectangular Dies
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Solution Overview
Problem
Conventional semiconductor package manufacturing methods, particularly sawing techniques, result in damage to semiconductor dies due to chipping and cracking, limiting the production of non-rectangular shapes and increasing the risk of damage during manufacturing.
Innovation Solution
Employing etching techniques to form notches in semiconductor wafers, which eliminates chipping and cracking, allowing for the production of non-rectangular die shapes and enhancing package reliability by using mold compounds to anchor to the sidewalls of these notches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If sawing techniques are used to manufacture semiconductor packages, then manufacturing efficiency is improved, but damage to semiconductor dies occurs due to chipping and cracking
Solution Approach 1:
The patent replaces the mechanical sawing process with a chemical etching process to form notches in the semiconductor wafer. This substitution eliminates the mechanical contact that causes chipping and cracking, thereby resolving the contradiction between manufacturing efficiency and die integrity.
Solution Approach 2:
The patent introduces an intermediary chemical etching process between the manufacturing steps. The etching process acts as a mediator that shapes the wafer without direct mechanical contact, preventing damage while maintaining manufacturing flow.
2Ease of manufacture
If conventional sawing techniques are used, then manufacturing process is simple, but non-rectangular die shapes cannot be produced
Solution Approach 1:
The patent changes the fundamental parameter of the shaping process from mechanical cutting to chemical etching. This parameter change enables the formation of complex non-rectangular shapes that cannot be achieved with conventional sawing, while the etching process remains relatively simple to implement.
3Manufacturing precision
If thicker pad layers are used to reduce spacing between conductors, then conductor spacing is improved, but pad layer complexity increases
Solution Approach 1:
The patent solves the spacing problem by transitioning from a two-dimensional planar arrangement to a three-dimensional vertical arrangement. Conductors are positioned at different heights (different z-dimension) above the pad layers, allowing reduced horizontal spacing while maintaining electrical isolation through the organic material.
Data Source
AI summary
Implementations of a semiconductor package may include a die; a first pad and a second pad, the first pad and the second pad each including a first layer and a second layer where the second layer may be thicker than the first layer. At least a first conductor may be directly coupled to the second layer of the first pad; at least a second conductor may be directly coupled to the second layer of the second pad; and an organic material may cover at least the first side of the die. The at least first conductor and the at least second conductor extend through openings in the organic material where a spacing between the at least first conductor and the at least second conductor may be wider than a spacing between the second layer of the first pad and the second layer of the second pad.