Semiconductor Package with Expanded Layer and Cover Wiring
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Solution Overview
Problem
The increasing demand for miniaturized, multifunctional, and high-capacity electronic devices requires semiconductor packages with improved connection reliability and reduced thickness to prevent interference between connection terminals, which existing fan-out semiconductor packages struggle to achieve effectively.
Innovation Solution
A semiconductor package design featuring a redistribution layer with multiple insulating layers and conductive structures, a surrounding expanded layer, and a cover wiring layer with a greater number of lower wiring layers and thicker upper wiring layers, respectively, to enhance connection reliability and minimize overall thickness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of connection terminals is increased for highly integrated semiconductor chips, then the functionality and capacity are improved, but interference between connection terminals occurs and reliability deteriorates
Solution Approach 1:
The patent transitions from a planar two-dimensional layout to a three-dimensional stacked architecture. Multiple semiconductor chips are vertically stacked with redistribution layers positioned between them, enabling increased connection terminals through vertical stacking while maintaining terminal spacing to prevent interference. This dimensional change allows higher integration without sacrificing connection reliability.
2Reliability
If the spacing between connection terminals is increased to prevent interference, then connection reliability is improved, but the device area increases and miniaturization is hindered
Solution Approach 1:
By stacking semiconductor chips vertically with redistribution layers in between, the patent achieves increased terminal spacing for reliability while maintaining a compact footprint. The vertical dimension accommodates the required spacing without expanding the horizontal package area, enabling miniaturization while preserving connection reliability.
Solution Approach 2:
The redistribution layers are nested between stacked semiconductor chips, creating a compact vertical structure. This nesting arrangement allows connection terminals to be distributed across multiple vertical levels with adequate spacing, preventing interference while maintaining a small overall package area suitable for miniaturized devices.
3Adaptability or versatility
If the number of wiring layers is increased to accommodate more connection terminals, then the capacity is improved, but the overall thickness increases
Solution Approach 1:
Redistribution layers are nested between stacked semiconductor chips, with each redistribution layer containing wiring patterns that connect terminals across adjacent chips. This nested arrangement accommodates multiple wiring layers within the vertical stack without significantly increasing overall thickness, as the wiring layers are integrated into the inter-chip spacing rather than adding external bulk.
Data Source
AI summary
A semiconductor package includes: a redistribution layer including a plurality of redistribution insulating layers, a plurality of redistribution line patterns that constitute lower wiring layers, and a plurality of redistribution vias that are connected to some of the plurality of redistribution line patterns while penetrating at least one of the plurality of redistribution insulating layers; at least one semiconductor chip arranged on the redistribution layer; an expanded layer surrounding the at least one semiconductor chip on the redistribution layer; and a cover wiring layer including at least one base insulating layer, a plurality of wiring patterns that constitute upper wiring layers, and a plurality of conductive vias that are connected to some of the plurality of wiring patterns while penetrating the at least one base insulating layer.