Semiconductor Package Heat Radiation via Exposed Lead Array

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Solution Overview

Problem

Semiconductor packages with large-area transistors, such as driver transistors, face heat radiation challenges due to their size, and existing solutions like metal-sealed packages are costly and complex, while resin-sealed packages with flip chip bonding struggle with effective heat dissipation.

Innovation Solution

A semiconductor package design using flip chip bonding with a resin seal, featuring a driver transistor and pads arranged in a specific array configuration, where the leads are partially exposed outside the resin to enhance heat radiation through wider voltage input and output leads and pads, allowing for efficient heat dissipation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Temperature

If metal material is used to seal the semiconductor package for heat radiation, then heat radiation is improved, but manufacturing complexity and cost increase

Engineering Contradiction:
Improveheat radiationVSAvoidsealing complexity
Core Design Contradiction:
TemperatureVSDevice complexity

Solution Approach 1:

The patent replaces expensive metal sealing materials with a cost-effective resin sealing material that achieves sufficient heat radiation performance through optimized lead array design, eliminating the need for complex metal sealing processes while maintaining thermal management effectiveness

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

Solution Approach 2:

The patent changes the sealing material from metal to resin and compensates for thermal performance by modifying the lead array parameters (increasing lead width and optimizing arrangement), thereby achieving heat radiation without metal sealing complexity

Inventive Principle:
Principle #35Parameter changes

2Temperature

If the IC chip is mounted on a die pad with exposed pads for heat radiation, then heat radiation is improved, but mounting area increases

Engineering Contradiction:
Improveheat radiationVSAvoidmounting area
Core Design Contradiction:
TemperatureVSArea of stationary object

Solution Approach 1:

The lead array serves dual functions: electrical connection and heat radiation. The leads are designed with sufficient width to act as both conductors and heat dissipation paths, eliminating the need for separate die pad exposure structures and reducing overall mounting area

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent merges the electrical connection function and heat radiation function into a single integrated structure (the lead array), where the leads simultaneously provide both electrical connectivity and thermal management, thereby reducing the required mounting area compared to separate die pad exposure approaches

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design improves heat radiation and minimizes voltage drop by using wider leads and pads, reducing manufacturing costs compared to metal-sealed packages and enhancing the thermal management of the semiconductor package.

Implementation Method 1

heat radiation can be improved by exposing the die pad outside an encapsulating resin

Methodology Applied
Scientific EffectThermal conduction: Conduction (thermal)

Data Source

PatentUS8415811B2Semiconductor package and electronic component package
Publication Date: 2013.04.09 NISSHINBO MICRO DEVICES INC
  • US8415811B2 patent drawing
  • US8415811B2 patent drawing
  • US8415811B2 patent drawing

AI summary

A semiconductor package includes an IC chip including a pad array having at least four pads, the pads including a voltage input pad and a voltage output pad disposed at edges of the pad array, a driver transistor disposed between the voltage input pad and the voltage output pad to receive an input voltage from the voltage input pad and output an output voltage to the voltage output pad, disposed in contact with an outer edge of the element arrangement region; and at least four leads on which the IC chip is mounted by flip chip bonding, disposed corresponding to the pads, formed in a lead array, the leads including a voltage input lead electrically connected to the voltage input pad and a voltage output lead electrically connected to the voltage output pad, disposed at edges of the lead array.