Top-Exposed Semiconductor Package with Exposed Metal Plates

Solution Overview

Problem

The existing top-exposed semiconductor packages have increased product costs, complex manufacturing processes, and reduced effective contact area due to the need for solder balls and spaces in the lead frame, which also enlarge the package size.

Innovation Solution

A semiconductor package design where a semiconductor chip with drain, source, and gate electrodes is mounted on a lead frame with separate metal plates attached using conductive adhesive layers, allowing for reduced package size and increased contact area, with a molding layer exposing specific surfaces for dual-channel heat dissipation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If solder balls are deposited on the chip surface and spaces are provided in the lead frame to prevent adhesive overflow and short-circuit, then short-circuit prevention is improved, but product cost increases, manufacturing process becomes complicated, effective contact area is reduced, and package size increases

Engineering Contradiction:

Improveshort-circuit preventionVSAvoidmanufacturing process complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The invention extracts and removes the solder balls from the chip surface and eliminates the spaces in the lead frame structure. By taking out these unnecessary elements, the manufacturing process is simplified while the short-circuit prevention function is maintained through the raised pattern design of the lead frame that inherently prevents adhesive overflow without requiring additional protective features.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

Instead of adding solder balls and spaces as protective measures, the invention inverts the approach by designing the lead frame with raised patterns that actively guide and contain the adhesive material. This inversion transforms the lead frame from a passive structure requiring additional protective elements to an active structure that inherently prevents short-circuits through its geometric design.

Inventive Principle:

Principle #13The other way round (Inversion)

2Reliability

If solder balls are deposited on the chip surface and spaces are provided in the lead frame, then short-circuit prevention is improved, but effective contact area of the source electrode is reduced

Engineering Contradiction:

Improveshort-circuit preventionVSAvoideffective contact area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The invention extracts and removes the solder balls from the chip surface and eliminates the spaces in the lead frame structure. By taking out these unnecessary elements, the manufacturing process is simplified while the short-circuit prevention function is maintained through the raised pattern design of the lead frame that inherently prevents adhesive overflow without requiring additional protective features.

Inventive Principle:

Principle #2Taking out (Extraction)

3Reliability

If spaces are provided in the lead frame for preventing short-circuit, then short-circuit prevention is improved, but package size increases

Engineering Contradiction:

Improveshort-circuit preventionVSAvoidpackage size

Core Design Contradiction:

ReliabilityVSVolume of stationary object

Solution Approach 1:

Instead of adding solder balls and spaces as protective measures, the invention inverts the approach by designing the lead frame with raised patterns that actively guide and contain the adhesive material. This inversion transforms the lead frame from a passive structure requiring additional protective elements to an active structure that inherently prevents short-circuits through its geometric design.

Inventive Principle:

Principle #13The other way round (Inversion)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design reduces package size, simplifies the manufacturing process, and maintains effective heat dissipation while minimizing the need for solder balls, thereby lowering costs and enhancing contact efficiency.

Implementation Method 1

a first conductive adhesive layer is attached on the chip to join the metal plate and the metal layer

Methodology Applied

Scientific EffectAdhesion: Adhesive

Implementation Method 2

a molding layer covering the lead frame and the chip

Methodology Applied

Scientific EffectPhysical containment: Physical Containment

Data Source

PatentUS9245831B1Top-exposed semiconductor package and the manufacturing method

Publication Date: 2016.01.26 ALPHA & OMEGA SEMICONDUCTOR (CAYMAN) LTD

AI summary

A semiconductor package includes a lead frame having a die paddle and a plurality of leads connected to die paddle, where each lead has a lead surface parallel to die paddle and is a continuous extension bending upward from die paddle. A semiconductor chip is mounted on die paddle, where drain metal layer covering a first surface of chip is connected to die paddle, and source metal layer and gate metal layer are located on a second surface opposite to first surface with gate metal layer located at one corner of the second surface. A source metal plate and a gate metal plate are attached on source metal layer and gate metal layer respectively. A molding layer covers lead frame, semiconductor chip, source metal plate and gate metal plate, where lead surface, top surfaces of source metal plate and gate metal plate are exposed from top surface of molding layer.