Semiconductor package
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Solution Overview
Problem
Existing semiconductor packages face challenges in achieving miniaturization, high performance, and large capacity while maintaining productivity and reliability, particularly in system-in-package (SiP) technology for interconnecting heterogeneous semiconductor chips.
Innovation Solution
A semiconductor package design featuring a redistribution structure with specific layers and connections, including redistribution patterns, chip structures, interconnection chips, through-vias, molds, and bump structures, optimized for improved electrical connectivity and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the chip body is made flexible to enable fine pitch interconnection patterns, then electrical connectivity is improved, but the risk of cracks increases
Solution Approach 1:
The patent applies beforehand cushioning by introducing a reinforcement layer between the flexible chip body and the interconnection patterns. This reinforcement layer is positioned in advance to prevent cracks from forming during subsequent processing and operation, thus cushioning against the inherent weakness of flexible materials while enabling fine pitch patterns for improved electrical connectivity
Solution Approach 2:
The patent uses composite materials by combining the flexible chip body material with a reinforcement layer material that has higher mechanical strength. This composite structure allows the chip body to maintain flexibility for fine pitch interconnection patterns while the reinforcement layer provides crack resistance, resolving the contradiction between flexibility and strength
2Reliability
If multiple insulating layers are added to protect interconnection patterns, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent applies local quality by positioning insulating layers specifically at critical locations where interconnection patterns are most vulnerable, rather than uniformly covering the entire chip. This targeted approach provides necessary protection while minimizing the overall number of layers and reducing device complexity
Solution Approach 2:
The patent implements nesting by integrating multiple functions into fewer layers. The insulating layers are designed to simultaneously provide electrical insulation, mechanical protection, and structural support, thus achieving reliable protection of interconnection patterns without proportionally increasing the number of discrete layers
Data Source
AI summary
A semiconductor package includes a redistribution structure including redistribution patterns, first and second chip structures on the redistribution structure and electrically connected to the redistribution patterns, a first mold covering at least a portion of each of the first and second chip structures, an interconnection chip including interconnection patterns electrically connected to the redistribution patterns and a plurality of insulating layers having third surfaces in which respective ones of the interconnection patterns are embedded, through-vias electrically connected to the redistribution patterns, a second mold covering at least a portion of each of the through-vias and the interconnection chip. Each third surface includes a first region, and a second region between the first region and an upper surface of the respective interconnection pattern embedded in the third surface. The second region defines a step between the first region and the upper surface of the interconnection pattern embedded in the third surface.