Semiconductor Package with Frame Recess and Through-Vias
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Solution Overview
Problem
Current semiconductor packages face challenges in improving yield and reducing manufacturing costs, while also optimizing signal line design, particularly in accommodating semiconductor chips with a large number of I/O terminals or compact sizes, and in direct mounting on electronic device mainboards.
Innovation Solution
A semiconductor package design featuring a frame with multiple wiring layers and a recess, a semiconductor chip with through-vias, and redistribution layers above and below the chip, along with an encapsulant filling the recess, allows for optimized signal line design and improved yield by reducing the impact of manufacturing defects on the expensive chip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a semiconductor chip with a large number of I/O terminals or compact size is used, then device functionality is improved, but manufacturing yield deteriorates and costs increase
Solution Approach 1:
The patent divides the semiconductor chip into multiple segments or modules, each with fewer I/O terminals. This segmentation allows each module to be manufactured separately with higher yield, then combined into a complete device. The frame structure with multiple wiring layers supports this modular approach by providing separate connection paths for different chip segments.
Solution Approach 2:
The patent transitions from a two-dimensional planar connection approach to a three-dimensional vertical connection approach using multiple wiring layers and via holes. This dimensional change allows I/O terminals to be distributed across multiple layers, reducing the density requirement on any single layer and improving manufacturability while maintaining high total I/O count.
2Adaptability or versatility
If the number of I/O terminals is increased, then device capability is improved, but signal line optimization becomes more difficult
Solution Approach 1:
The patent uses multiple wiring layers stacked vertically to distribute I/O terminals across three dimensions. This allows signal lines to be routed on different layers, reducing crosstalk and simplifying signal line design despite having a large total number of I/O terminals. The frame structure with its plurality of wiring layers provides the necessary vertical routing capacity.
Solution Approach 2:
The frame structure acts as an intermediary between the semiconductor chip and the external environment. It provides a standardized interface with organized signal lines that simplifies connection to the mainboard, while the chip itself can have any number of I/O terminals arranged optimally for its function. The redistribution layers in the frame mediate the connection between chip pads and external signals.
3Ease of manufacture
If direct mounting on electronic device mainboards is implemented, then assembly process is simplified, but manufacturing precision requirements increase
Solution Approach 1:
The patent incorporates mounting structures and alignment features directly into the frame during the packaging process, before the chip is mounted on the mainboard. The frame is pre-assembled with the semiconductor chip and encapsulant, creating a complete module with built-in alignment references. This preliminary preparation simplifies the subsequent mainboard mounting process and reduces precision requirements during final assembly.
Data Source
AI summary
A semiconductor package includes a frame having a recess on which a stopper layer is disposed, a semiconductor chip including a body having a first surface on which a connection pad is disposed and a second surface opposing the first surface, and a through-via penetrating through at least a portion of a region between the first surface and the second surface, the second surface facing the stopper layer, an encapsulant covering at least a portion of each of the frame and the semiconductor chip and filling at least a portion of the recess, a first connection structure disposed on a lower side of the frame and on the first surface of the semiconductor chip and including a first redistribution layer, and a second connection structure disposed on an upper side of the frame and on the second surface of the semiconductor chip and including a second redistribution layer.