3D Semiconductor Package Assembly Fusion Bonding
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Solution Overview
Problem
Conventional 3D semiconductor packages face limitations in integrating multiple dies of varying sizes and functions, leading to reduced design flexibility and increased manufacturing yield loss due to the inclusion of defective components.
Innovation Solution
A 3D system-in-package (SIP) semiconductor package assembly is developed, where multiple known-good components or dies are separately fabricated and integrated using a method involving carrier substrates, molding compounds, redistribution layers, and fusion bonding, allowing for flexible integration of components of different sizes and functions without the need for additional bonding structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional 3D semiconductor packaging technology is used to integrate multiple dies, then integration density is improved, but design flexibility is reduced because dies are limited to the same size
Solution Approach 1:
The patent segments the integration process into two distinct phases: (1) separate fabrication and testing of individual dies on their own carrier substrates, and (2) subsequent integration of only known-good dies into the final package. This segmentation allows each die to be optimized independently for size and function while maintaining high integration density in the final assembly.
Solution Approach 2:
The patent transitions from traditional 2D packaging to 3D stacked packaging, utilizing the vertical dimension to integrate multiple dies of varying sizes. By stacking dies vertically rather than arranging them in a single plane, the system achieves higher integration density while accommodating dies with different footprints and functions.
2Adaptability or versatility
If conventional 3D semiconductor packages integrate multiple dies, then functionality is enhanced, but manufacturing yield is reduced due to inclusion of defective components
Solution Approach 1:
The patent performs preliminary testing and selection of dies on their respective carrier substrates before integration. By identifying and selecting only known-good dies in advance, the system ensures high manufacturing yield in the final package while maintaining enhanced functionality through the integration of multiple specialized dies.
Solution Approach 2:
Carrier substrates serve as intermediary platforms for fabricating, testing, and storing individual dies before final integration. These intermediaries allow for quality control and selection processes to occur separately from the main packaging operation, ensuring that only functional dies are integrated into the final multi-die package.
3Reliability
If additional bonding structures are used to integrate dies in conventional 3D packages, then connection reliability is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent merges the die integration process with the packaging process by directly attaching selected dies to the package substrate without requiring separate bonding structures. This consolidation reduces structural complexity and manufacturing steps while maintaining reliable electrical and mechanical connections between dies and the package.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances design flexibility, reduces manufacturing costs, and significantly improves yield by ensuring only good components are used, while also reducing the thickness and signal path length, thereby enhancing device performance.
Implementation Method 1
a first molding compound 120A surrounding the sidewalls of the first components 110A
Implementation Method 2
bonding the first package 10A and the second package 10B to each other using a fusion bonding method
Data Source
Figure 1A
Figure 1B
Figure 1C
AI summary
A semiconductor package assembly is provided. The semiconductor package assembly includes a first semiconductor package. The first semiconductor package includes a first semiconductor die. A first redistribution layer (RDL) structure is coupled to the first semiconductor die and includes a first conductive trace. The semiconductor package assembly also includes a second semiconductor package bonded to the first semiconductor package. The second semiconductor package includes a second semiconductor die. An active surface of the second semiconductor die faces an active surface of the first semiconductor die. A second RDL structure is coupled to the second semiconductor die and includes a second conductive trace. The first conductive trace is in direct contact with the second conductive trace.