Semiconductor Package Gap Control With Minimal Adhesive Film Overhang
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Solution Overview
Problem
Current semiconductor packages face challenges in miniaturization and weight reduction while maintaining high performance, particularly in achieving uniform gaps and efficient stacking of semiconductor chips, which affects yield and productivity.
Innovation Solution
A semiconductor package design that includes a base chip with a semiconductor chip mounted on top, connected by bumps and an adhesive film, where the adhesive film's outer portion protrudes minimally and uniformly surrounds the chip, ensuring consistent separation distances and improved wetting of bumps through a foil lamination and pressure-reflow process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the adhesive film outer portion protrudes significantly beyond the chip edges, then the chip is well-supported and positioned, but the package height increases and miniaturization is compromised
Solution Approach 1:
The patent optimizes the adhesive film outer portion width to 50 μm or less, transforming it from a significant protrusion to a minimal one. This parameter change allows the adhesive film to provide sufficient support and positioning while minimizing the increase in package height, thus resolving the contradiction between reliability and miniaturization.
2Strength
If the adhesive film outer portion width is large, then the chip is well-supported during mounting, but warpage increases and manufacturing precision deteriorates
Solution Approach 1:
The patent specifies that the adhesive film outer portion width should be 50 μm or less, changing this critical parameter to achieve a balance between support strength and warpage control. This optimized width provides adequate mechanical support during mounting while minimizing differential stress that causes warpage, thereby maintaining manufacturing precision.
3Reliability
If multiple chips are stacked with large adhesive film protrusions, then each chip is securely fixed, but the overall package complexity and volume increase
Solution Approach 1:
By reducing the adhesive film outer portion width to 50 μm or less in multi-chip stacks, the patent minimizes the cumulative volume increase that would occur with each additional chip. This parameter optimization allows secure fixation of multiple chips while controlling the overall package volume for miniaturization.
4Length of stationary object
If the adhesive film outer portion is minimal (50 μm or less), then miniaturization is achieved, but chip positioning and support may be compromised
Solution Approach 1:
The patent identifies 50 μm as the optimal parameter threshold for the adhesive film outer portion width. At this dimension, the adhesive film provides sufficient positioning accuracy and support while minimizing package height increase. This precise parameter control resolves the contradiction between miniaturization and positioning reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances yield and productivity by maintaining uniform gaps between chips, reducing warpage, and minimizing defects, thereby achieving improved reliability and performance in semiconductor packages.
Implementation Method 1
an adhesive film between the base chip and the semiconductor chip, the adhesive film fixing the semiconductor chip to the base chip
Implementation Method 2
a plurality of bumps on the connection pads, the plurality of bumps electrically connecting the base chip to the semiconductor chip
Data Source
AI summary
A semiconductor package including a base chip; a semiconductor chip having a lower surface on which connection pads are disposed, the semiconductor chip being mounted on an upper surface of the base chip; a plurality of bumps on the connection pads and electrically connecting the base chip to the semiconductor chip; an adhesive film between the base chip and the semiconductor chip and fixing the semiconductor chip to the base chip; and an encapsulant on the base chip and encapsulating the semiconductor chip, wherein the semiconductor chip includes a central portion spaced apart from the upper surface of the base chip by a first distance, and an edge portion spaced apart from the upper surface of the base chip by a second distance, the edge portion being outside of the central portion, and a ratio of the second distance to the first distance is about 0.8 to about 1.0.