Semiconductor Package Stacking With Gap-Fill Bonding to Prevent Voids
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Solution Overview
Problem
In multi-chip semiconductor packages, the accumulation of bonding interface topology leads to voids and deteriorates bonding quality, especially when stacking multiple chips, which increases costs due to the need for extensive topology initialization in the wafer support system.
Innovation Solution
A semiconductor package design featuring sequentially stacked core die stacks with gap filling portions that are directly bonded to each other, using hybrid bonding and thermal compression processes to prevent voids at the bonding interface, and including a buffer die with insulating layers and bonding pads for efficient chip stacking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If pad-to-pad direct bonding is performed without solder bumps in die to wafer bonding process, then manufacturing cost is reduced and bonding strength is improved, but unbonded areas (voids) occur due to accumulation of bonding interface topology as the number of stacked chips increases
Solution Approach 1:
The patent introduces a gap filling portion as an intermediary element between stacked semiconductor chips. This gap filling portion fills the voids that accumulate at bonding interfaces during multi-chip stacking, thereby maintaining bonding quality and reliability while allowing the use of direct bonding without solder bumps.
Solution Approach 2:
The gap filling portion is prepared in advance and positioned at the bonding interface before the actual bonding process. This preliminary action prevents void formation from occurring in the first place, rather than attempting to correct it after bonding has taken place.
2Productivity
If the number of stacked chips is increased to achieve higher integration, then device functionality is improved, but unbonded areas (voids) accumulate at bonding interfaces deteriorating bonding quality
Solution Approach 1:
The gap filling portion serves as a mediator that enables higher chip stacking density by preventing void accumulation at each bonding interface. This allows the system to achieve higher productivity through increased stacking while maintaining reliable bonds throughout the stack.
Solution Approach 2:
The bonding interface is segmented into multiple regions by introducing the gap filling portion, which divides the continuous bonding interface into discrete segments. This segmentation prevents the accumulation of voids across the entire interface, allowing for higher stacking densities without compromising overall bonding quality.
3Reliability
If extensive topology initialization is performed in the wafer support system to maintain bonding quality during high-level chip stacking, then bonding quality is maintained, but manufacturing cost increases
Solution Approach 1:
The gap filling portion acts as a simple intermediary structure that maintains bonding quality without requiring complex topology initialization processes. This approach preserves reliability while avoiding the high manufacturing costs associated with extensive wafer support system modifications.
Solution Approach 2:
The gap filling portion is a simple, cost-effective structure that replaces the need for expensive and complex topology initialization processes. It is a disposable element that is easily incorporated into the manufacturing process without requiring significant investment in wafer support system infrastructure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents voids at the bonding interface during high-level chip stacking, reducing costs associated with the wafer support system and enhancing bonding quality by directly bonding gap filling portions and ensuring strong bonding interfaces.
Implementation Method 1
using hybrid bonding and thermal compression processes to prevent voids at the bonding interface
Implementation Method 2
using hybrid bonding and thermal compression processes to prevent voids at the bonding interface
Data Source
AI summary
A semiconductor package includes a buffer die, a first core die stack stacked on the buffer die, the first core die stack including at least one first intermediate core and a first gap filling portion covering an outer surface of the at least one first intermediate core, and a second core die stack stacked on the first core die stack, the second core die stack including at least one second intermediate core and a second gap filling portion covering an outer surface of the at least one second intermediate core. The first gap filling portion and the second gap filling portion are directly bonded to each other.