Semiconductor Package Layout to Reduce Gate-Loop Magnetic Coupling
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Solution Overview
Problem
Magnetic fields generated by current flow in semiconductor transistors induce unwanted coupling, leading to increased switching losses and reduced efficiency, particularly in high-speed devices like SiC or GaN transistors.
Innovation Solution
A semiconductor package and printed circuit board design that includes specific configurations of external contacts and electrical connectors to minimize or utilize magnetic coupling, such as rearranging pinouts, using magnetic shielding, increasing distances between leads, and altering wire bond configurations to reduce magnetic interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the Kelvin emitter configuration is used to reduce switching losses and increase switching speed, then switching efficiency is improved, but magnetic coupling between the source load path and gate control loop increases, leading to induced voltage and higher switching losses
Solution Approach 1:
The patent extracts and separates the gate control loop from the source load path by using dedicated sense source/sense emitter connections. This physical separation removes the harmful magnetic coupling effect from the gate control path while maintaining the high-speed switching capability through the Kelvin emitter configuration.
Solution Approach 2:
The patent introduces sense source/sense emitter as an intermediary element between the source and the gate control loop. This intermediary provides a dedicated low-impedance path for sense current that is magnetically isolated from the main load current, thereby reducing induced voltage in the gate control path.
2Loss of energy
If external contacts are arranged to reduce magnetic coupling, then switching losses are reduced, but device complexity increases due to additional sense source/sense emitter connections
Solution Approach 1:
The sense source/sense emitter connections serve multiple functions: they provide magnetic isolation for the gate control loop, establish a low-impedance sense path, and maintain compatibility with standard Kelvin emitter configurations. This multi-functionality reduces switching losses without proportionally increasing device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed design effectively reduces magnetic coupling, thereby enhancing switching speed and efficiency of semiconductor transistors by mitigating the negative effects of magnetic fields on the gate control loop.
Implementation Method 1
the magnetic fields generated by the source load path are coupled into the logic path consisting of gate and Kelvin emitter and induce a voltage/current
Data Source
Figure 1A~2C
Figure 3~5
Figure 6~7B
AI summary
A semiconductor package (20, 30, 40, 50) comprises a semiconductor transistor circuit comprising a semiconductor transistor die comprising die terminals, including a collector/drain, a source/emitter, a sense source/sense emitter, a gate, and a load path, a driver line connected with the gate, and a gate control loop in which the a sense source/sense emitter is connected with the driver line, a plurality of external contacts comprising at least one first external contact (D/C) connected with the drain/collector, at least one second external contact (S/El) connected with the source/emitter, a third external contact (K/E2) connected with the a sense source/sense emitter , and a fourth external contact (G) connected with the gate, wherein the plurality of external contacts are arranged or configured to reduce or utilize the magnetic coupling induced by a load current flowing through the load path.