Semiconductor Package with Connection Dam and Glass Layer

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Solution Overview

Problem

Semiconductor packages, particularly image sensors, face challenges in maintaining strength to prevent cracks and efficiently manufacturing compact, high-reliability components with reduced keep-out-zones (KoZ) for increased integration and reliability.

Innovation Solution

A semiconductor package design featuring a silicon layer with a molding layer and a connection dam that connects the silicon layer to glass, along with a micro-lens array, and a method of fabrication that includes coupling wafers, forming via holes, and wafer molding to create a chip-scale package with enhanced mechanical strength and reduced KoZ.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Strength

If a conventional semiconductor package structure is used, then the manufacturing process is relatively simple, but the mechanical strength is insufficient and cracks occur

Engineering Contradiction:
Improvemechanical strengthVSAvoidpackage structure complexity
Core Design Contradiction:
StrengthVSDevice complexity

Solution Approach 1:

The patent employs a composite structure consisting of a silicon layer, molding layer, and glass layer bonded together. This multi-material composite approach significantly enhances the mechanical strength of the semiconductor package while distributing stress across different materials with complementary properties, thereby preventing cracks without excessive complexity

Inventive Principle:
Principle #40Composite materials

Solution Approach 2:

The package structure is divided into distinct functional layers (silicon layer, molding layer, glass layer) with clear interfaces. This segmentation allows each layer to perform its specific function optimally while being bonded through connection dams, achieving high strength through structured assembly rather than monolithic complexity

Inventive Principle:
Principle #1Segmentation

2Productivity

If the keep-out-zone (KoZ) size is reduced for increased integration, then component integration efficiency improves, but the structural strength and reliability decrease

Engineering Contradiction:
Improveintegration efficiencyVSAvoidpackage reliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The composite structure of silicon, molding, and glass layers provides distributed structural support throughout the package. This allows the keep-out-zone to be minimized for higher integration density while the surrounding composite materials compensate for the reduced KoZ area, maintaining overall reliability through the collective strength of the multi-layer system

Inventive Principle:
Principle #40Composite materials

Solution Approach 2:

The patent transitions from a two-dimensional planar support structure to a three-dimensional multi-layer composite structure. By adding vertical layering with connection dams bonding silicon, molding, and glass layers together, structural strength is maintained in the vertical dimension even when horizontal keep-out-zone area is reduced for integration

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Volume of moving object

If the silicon layer is made thinner to reduce package size, then compactness improves, but the mechanical strength decreases and cracks occur

Engineering Contradiction:
Improvepackage sizeVSAvoidsilicon layer strength
Core Design Contradiction:
Volume of moving objectVSStrength

Solution Approach 1:

The thin silicon layer is bonded between a molding layer and a glass layer to form a composite sandwich structure. This configuration allows the silicon layer to be made thinner for compactness while the thicker molding and glass layers provide the necessary mechanical strength and crack prevention, with connection dams ensuring strong inter-layer bonding

Inventive Principle:
Principle #40Composite materials

Data Source

PatentUS11710757B2Semiconductor package and method of fabricating the same
Publication Date: 2023.07.25 SAMSUNG ELECTRONICS CO LTD
  • US11710757B2 patent drawing
  • US11710757B2 patent drawing
  • US11710757B2 patent drawing

AI summary

Disclosed are semiconductor packages and methods of fabricating the same. The semiconductor package comprises a molding layer, a silicon layer on the molding layer, a glass upwardly spaced apart from the silicon layer, and a connection dam coupled to the silicon layer and connecting the silicon layer to the glass. The silicon layer includes a silicon layer body, a silicon layer via extending vertically in the silicon layer body, and a micro-lens array on a top surface of the silicon layer body. A bottom surface of the silicon layer body contacts a top surface of the molding layer. The molding layer includes a molding layer body, a molding layer via that extends vertically in the molding layer body and has electrical connection with the silicon layer via, and a connection ball connected to a bottom surface of the molding layer via.