Semiconductor Package with Asymmetric Glue Encapsulation

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Solution Overview

Problem

Current semiconductor packaging technologies face challenges in efficiently integrating and connecting multiple integrated circuit components on a single wafer, particularly in achieving reliable electrical connections and adequate encapsulation for advanced packaging requirements, such as thermal conductivity and mechanical stability.

Innovation Solution

The method involves using a carrier with a debond layer and a buffer layer, where integrated circuit components are adhered via connecting films, encapsulated with insulating materials, and connected through a redistribution circuit structure, allowing for improved planarization and electrical connectivity, and the use of conductive pillars for enhanced packaging.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiple integrated circuit components are integrated on a single wafer, then productivity increases, but manufacturing precision deteriorates due to challenges in achieving reliable electrical connections and adequate encapsulation

Engineering Contradiction:
Improveintegration efficiencyVSAvoidconnection reliability
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent segments the wafer into multiple individual component regions, each with its own encapsulation and connection structure. This allows each component to be processed and connected independently while maintaining high integration density, thus preserving manufacturing precision despite increased productivity requirements

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces intermediary structures including connecting films between components, insulating encapsulation materials, and redistribution circuit structures. These intermediaries facilitate reliable electrical connections between multiple components while maintaining manufacturing precision through controlled interfaces and standardized connection protocols

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If advanced packaging requirements are implemented, then reliability improves, but device complexity increases

Engineering Contradiction:
Improveelectrical connection reliabilityVSAvoidpackaging structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements universal packaging structures that can accommodate multiple integrated circuit components of different types and sizes. The standardized connecting films, insulating encapsulation, and redistribution circuit structures serve multiple functions simultaneously: electrical connection, mechanical support, thermal management, and protection, thereby improving reliability without proportionally increasing complexity

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent merges multiple functions into integrated structures: the insulating encapsulation material simultaneously provides electrical isolation, mechanical protection, and thermal management; the redistribution circuit structure combines electrical connection with structural support. This merging reduces overall device complexity while maintaining advanced packaging reliability requirements

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS11205603B2Semiconductor package and method manufacturing the same
Publication Date: 2021.12.21 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11205603B2 patent drawing
  • US11205603B2 patent drawing
  • US11205603B2 patent drawing

AI summary

A semiconductor package including at least one integrated circuit component and a glue material is provided. The at least one integrated circuit component has a top surface with conductive terminals and a backside surface opposite to the top surface. The glue material encapsulates the at least one integrated circuit component, wherein a first lateral thickness of the glue material is smaller than a second lateral thickness of the glue material, the second lateral thickness is parallel to the first lateral thickness, and the first lateral thickness is substantially coplanar with the top surface.