Semiconductor Package Ground-Line Layout for Signal Integrity
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Solution Overview
Problem
The increasing storage capacity and functional complexity of semiconductor chips require semiconductor packages to be thinner, lighter, and with improved operation performance, while existing designs face challenges in managing signal interference.
Innovation Solution
The semiconductor package incorporates ground line patterns at the same level as signal line patterns, with some extending between them, to suppress signal interference and enhance signal integrity (SI).
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ground line patterns are placed at the same level as signal line patterns and extend between them, then signal integrity is improved, but device complexity increases
Solution Approach 1:
The patent transitions from traditional multi-layer stacked ground and signal lines to a planar configuration where ground line patterns extend between signal line patterns at the same level within the substrate insulating layer. This dimensional reorganization suppresses signal interference while maintaining manufacturing feasibility.
2Weight of moving object
If semiconductor package size is reduced to meet thin and light requirements, then weight and volume are improved, but signal interference management becomes more difficult
Solution Approach 1:
The patent applies different functional qualities to different regions of the substrate insulating layer: ground line patterns are strategically positioned between signal line patterns to provide localized shielding and suppress interference, while signal line patterns maintain their transmission function. This local differentiation enables effective signal interference management within a compact package structure.
Data Source
AI summary
A semiconductor package includes a semiconductor chip including a semiconductor substrate having an active layer, ground chip pads on the semiconductor substrate, and signal chip pads on the semiconductor substrate and a package substrate supporting the semiconductor chip, the package substrate including a substrate insulating layer, a plurality of signal line patterns extending in the substrate insulating layer and electrically connected to the signal chip pads, and a plurality of ground line patterns extending in the substrate insulating layer at a same level as a level of the plurality of signal line patterns and electrically connected to the ground chip pads. At least one of the plurality of ground line patterns extends between the plurality of signal line patterns.