Semiconductor Package Grounding Layout for Low-Crosstalk Die Connection

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Solution Overview

Problem

Existing semiconductor package structures face challenges in reducing crosstalk and parasitic inductance between conductive paths, particularly as integration density increases.

Innovation Solution

The introduction of an inter-die connector that directly connects the grounding lines of adjacent dies without additional redistribution layers, effectively reducing the conductive path and minimizing crosstalk and parasitic inductance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If additional redistribution layers are used to connect grounding lines of adjacent dies, then electrical connection is achieved, but crosstalk and parasitic inductance increase

Engineering Contradiction:
Improveelectrical connection qualityVSAvoidcrosstalk and parasitic inductance
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent extracts and eliminates the intermediate redistribution layers from the grounding connection path between adjacent dies. By directly connecting the grounding lines of first and second adjacent dies through the inter-die connector without passing through redistribution layers, the harmful inductance and crosstalk generated by these intermediate layers are removed, while maintaining reliable electrical connection.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The inter-die connector serves as a dedicated intermediary component specifically designed to connect grounding lines between adjacent dies. This specialized connector provides a low-inductance, direct connection path that bypasses the general-purpose redistribution layers, thereby reducing parasitic effects while ensuring proper electrical connection.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If integration density is increased by reducing minimum feature size, then more components are integrated into a given area, but crosstalk between conductive paths increases

Engineering Contradiction:
Improveintegration densityVSAvoidcrosstalk between conductive paths
Core Design Contradiction:
ProductivityVSObject-generated harmful factors

Solution Approach 1:

The patent segments the grounding connection function from the general signal distribution function by introducing a dedicated inter-die connector. This segmentation allows grounding lines to have their own direct connection path independent of redistribution layers, reducing crosstalk between signal paths while maintaining high integration density through efficient space utilization.

Inventive Principle:
Principle #1Segmentation

3Ease of manufacture

If conventional package structures are used, then manufacturing is simpler, but crosstalk between conductive paths increases

Engineering Contradiction:
Improvemanufacturing simplicityVSAvoidcrosstalk between conductive paths
Core Design Contradiction:
Ease of manufactureVSObject-generated harmful factors

Solution Approach 1:

The patent merges the inter-die connector formation process with the existing bump structure fabrication process. The inter-die connector is formed as part of the same manufacturing sequence that creates the bumps, integrating the grounding connection function into the established manufacturing flow without requiring entirely new process equipment or methods, thus maintaining ease of manufacture while reducing crosstalk.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentEP3657534B1Semiconductor package structure and method for forming the same
Publication Date: 2025.04.02 MEDIATEK INC
  • EP3657534B1 patent drawingFigure 1
  • EP3657534B1 patent drawingFigure 2
  • EP3657534B1 patent drawingFigure 3

AI summary

A semiconductor package structure includes a first semiconductor die (100A) and a second semiconductor die (200B) neighboring the first semiconductor die. The first semiconductor die includes a first edge, a second edge opposite the first edge, and a first metal layer exposed (310) from the second edge. The second semiconductor includes a third edge neighboring the second edge of the first semiconductor die, a fourth edge opposite the third edge, and a second metal layer (320) exposed from the third edge. The first metal layer of the first semiconductor die is electrically connected (500) to the second metal layer of the second semiconductor die.