Semiconductor Package Layout With Through Openings for HBM Heat Dissipation
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Solution Overview
Problem
The 2.5D semiconductor package faces challenges in heat dissipation due to the exposed upper surface of high-bandwidth memory (HBM) and potential cracking issues from the wide area underfill material, which hinders effective heat dissipation and structural integrity.
Innovation Solution
A semiconductor package design incorporating a redistribution structure with through openings for semiconductor stacking structures, a heat dissipation structure with through openings for efficient heat discharge, and a molding material to manage stress and prevent cracking, enhancing thermal characteristics and integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the HBM is vertically stacked to increase integration density, then the integration density is improved, but the heat dissipation capability deteriorates due to the exposed upper surface
Solution Approach 1:
The patent transitions from a planar 2.5D package structure to a three-dimensional structure by introducing vertical through-openings in the molding material. This allows heat dissipation paths to extend in the vertical dimension, enabling heat sinks to contact both the logic die and HBM stacks, thereby improving heat dissipation capability while maintaining high integration density.
2Quantity of substance
If the logic die and HBM are disposed side by side on the silicon interposer to achieve high integration density, then the integration density is improved, but the structural reliability deteriorates due to bending and cracking in the underfill material
Solution Approach 1:
The patent segments the molding material into multiple regions by introducing through-openings, creating distinct zones that accommodate different components (logic die, HBM stacks) independently. This segmentation reduces the continuous stress distribution in the underfill material, preventing bending and cracking while maintaining high integration density.
3Quantity of substance
If the HBM has greater height than the logic die to achieve vertical stacking, then the integration density is improved, but the heat dissipation capability deteriorates due to the exposed upper surface of HBM
Solution Approach 1:
The patent implements a nested structure where heat sinks are positioned within the molding material to contact the HBM stacks from the sides, and additional heat dissipation structures are nested within through-openings. This nested arrangement allows efficient heat dissipation from the exposed upper surfaces of HBM while maintaining compact vertical stacking for high integration density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively dissipates heat generated in the logic die and improves the structural reliability of the semiconductor package by allowing efficient heat discharge and reducing stress, thus expanding the allowable height range for semiconductor stacking structures.
Implementation Method 1
a heat dissipation structure on the semiconductor structure, the heat dissipation structure including a plurality of through openings
Data Source
AI summary
Provided a semiconductor package including a redistribution structure, a semiconductor structure on the redistribution structure, a plurality of semiconductor stacking structures on the redistribution structure, the plurality of semiconductor stacking structures being adjacent to the semiconductor structure, and a height of each of the plurality of semiconductor stacking structures being greater than a height of the semiconductor structure, and a heat dissipation structure on the semiconductor structure, the heat dissipation structure including a plurality of through openings, wherein each semiconductor stacking structure among the plurality of semiconductor stacking structures is positioned within a corresponding through opening among the plurality of through openings, and wherein an upper surface of each of the plurality of semiconductor stacking structures is exposed through the corresponding through opening.