Semiconductor Package Layout With Exposed Chip Surfaces for Heat Dissipation
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Solution Overview
Problem
As electronic devices become lighter and more high-performance, the thermal resistance in stacked semiconductor packages increases, leading to a decrease in semiconductor chip performance due to inadequate heat dissipation.
Innovation Solution
A semiconductor package design that exposes upper and side surfaces of semiconductor chips through an encapsulant, forming a hexahedral structure, which enhances heat dissipation by increasing the exposed area and reducing thermal resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple semiconductor chips are stacked and molded within a semiconductor package, then integration density increases, but thermal resistance increases leading to decreased chip performance
Solution Approach 1:
The patent transitions from vertical stacking to horizontal arrangement of semiconductor chips on the substrate. This dimensional change allows heat to dissipate more effectively across a larger surface area while maintaining high integration density, thereby resolving the thermal resistance issue associated with stacked configurations.
Solution Approach 2:
The patent divides the semiconductor package into multiple independent chip regions with exposed surfaces, rather than fully enclosing all chips. This segmentation allows different parts of the package to serve different functions - some chips are fully enclosed while others have exposed surfaces for heat dissipation, enabling simultaneous high integration and effective thermal management.
2Reliability
If semiconductor chips are fully enclosed by encapsulant, then protection is improved, but heat dissipation deteriorates
Solution Approach 1:
The patent applies different encapsulation qualities to different chips within the same package. Some chips are fully enclosed by the encapsulant for maximum protection, while other chips have exposed surfaces that allow heat dissipation. This local differentiation of encapsulation quality enables simultaneous achievement of protection and heat dissipation in different regions of the package.
3Temperature
If chip surfaces are exposed from encapsulant, then heat dissipation improves, but manufacturing complexity increases due to wire exposure risks
Solution Approach 1:
The patent performs preliminary planning in the chip arrangement and encapsulation design to prevent wire exposure during manufacturing. By carefully designing which chip surfaces should be exposed and which should be enclosed, and by controlling the encapsulation depth and positioning, the manufacturing process is simplified rather than complicated, as wire exposure issues are prevented by design rather than requiring additional corrective steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design improves heat dissipation characteristics by reducing thermal resistance and preventing wire exposure during manufacturing, thereby maintaining chip performance.
Implementation Method 1
thermal resistance increases, which may cause a decrease in performance of the semiconductor chips. Accordingly, a semiconductor package technology that may effectively dissipate heat generated by semiconductor chips is required
Data Source
AI summary
A semiconductor package includes: a substrate; four semiconductor chips spaced apart from each other on the substrate, each of the four semiconductor chips including an active surface that is perpendicular to an upper surface of the substrate; wires extending from the active surface of each of the four semiconductor chips, respectively, and electrically connecting the four semiconductor chips and the substrate; and an encapsulant on the substrate and surrounding the four semiconductor chips, wherein upper surfaces and first side surfaces of each of the four semiconductor chips are exposed from the encapsulant.