Semiconductor Package Layout for Heat Dissipation and Insulation

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Solution Overview

Problem

Conventional semiconductor devices with metal layer wiring suffer from degraded heat dissipation properties due to increased thermal resistance and insulation issues, particularly when terminals are formed on the lateral surface, leading to inefficient heat dissipation from the semiconductor element to the outside.

Innovation Solution

A semiconductor device design featuring a conductive layer positioned above the terminal portion with a resin layer having openings for direct electrical connection to the semiconductor element, reducing the distance to the sealing resin and enhancing heat dissipation by allowing efficient conduction of heat from the semiconductor element to the outside through the conductive layers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the terminal is arranged at a connectable position of the upper portion of the metal layer and entirely sealed with sealing resin, then insulation properties are secured, but the distance from the metal layer to the sealing resin increases, degrading heat dissipation properties

Engineering Contradiction:
Improveinsulation propertiesVSAvoidheat dissipation properties
Core Design Contradiction:
ReliabilityVSTemperature

Solution Approach 1:

The patent positions the upper surface of the metal layer above the upper surface of the terminal in the vertical dimension, creating a stepped configuration. This dimensional arrangement allows the metal layer to be closer to the sealing resin while the terminal remains properly insulated, resolving the contradiction between insulation requirements and heat dissipation efficiency

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent applies different spatial arrangements to different components: the terminal is positioned lower for insulation, while the metal layer is positioned higher for heat dissipation. This localized differentiation of component positions optimizes both insulation properties and thermal performance simultaneously

Inventive Principle:
Principle #3Local quality

2Reliability

If bonding wire is used for gate electrode and sensing electrode, then electrical connection is achieved, but the thickness of sealing resin increases, leading to increased distance and degraded heat dissipation

Engineering Contradiction:
Improveelectrical connectionVSAvoidheat dissipation properties
Core Design Contradiction:
ReliabilityVSTemperature

Solution Approach 1:

The patent merges the functions of the metal layer to serve both as an electrical interconnect and as a thermal management component. By having the metal layer extend above the terminal surface and contact the sealing resin, it simultaneously provides electrical connection and creates a low-thermal-resistance path for heat dissipation, eliminating the need for additional sealing resin thickness

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design improves heat dissipation properties by reducing the thermal resistance and enhancing cooling efficiency, maintaining the semiconductor device's reliability even under high-temperature conditions.

Implementation Method 1

heat dissipation properties by reducing the thermal resistance and enhancing cooling efficiency

Methodology Applied
Scientific EffectThermal conduction: Conduction (thermal)

Data Source

PatentUS11784105B2Semiconductor device and power converter
Publication Date: 2023.10.10 MITSUBISHI ELECTRIC CORP
  • US11784105B2 patent drawing
  • US11784105B2 patent drawing
  • US11784105B2 patent drawing

AI summary

A semiconductor device includes: a circuit member including a planar portion; a terminal portion formed above the front surface of the planar portion of the circuit member and parallel to the planar portion; a semiconductor element which has an upper surface located below an upper surface of the terminal portion and is formed on the front surface of the planar portion of the circuit member; a resin layer arranged on the semiconductor element and having first openings through which the semiconductor element is exposed; a conductive layer arranged on the resin layer, including an upper surface located above the upper surface of the terminal portion, and joined to the semiconductor element through the first openings; and a sealing member including an upper surface parallel to the planar portion and integrally sealing the circuit member, the semiconductor element, the resin layer, the conductive layer, and part of the terminal portion.