Redistribution Semiconductor Package for Heat Dissipation and Routing
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Solution Overview
Problem
Current semiconductor packages face challenges in achieving improved thermal properties, which are crucial for preventing operating delays and enhancing reliability, especially as they strive for compact size and low manufacturing costs.
Innovation Solution
The semiconductor package design incorporates a main semiconductor chip with a first thickness and at least one semiconductor device of a second thickness, utilizing a first and second redistribution substrate with molding layers to expose top and lateral surfaces, and a mold via to connect these substrates, facilitating effective heat dissipation and signal/power transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If a conventional semiconductor package structure is used, then manufacturing cost and compact size are achieved, but thermal properties are insufficient leading to operating delays and reduced reliability
Solution Approach 1:
The invention divides the semiconductor package into multiple functional layers including a substrate, molding layer, and redistribution substrate, with each layer serving specific thermal and electrical functions. This segmentation allows optimized thermal management in each layer while maintaining overall package integrity and reliability.
Solution Approach 2:
The invention introduces a mold via structure as an intermediary element that penetrates the molding layer to establish thermal and electrical connection between the semiconductor chip and the redistribution substrate. This intermediary pathway enables effective heat dissipation and signal transmission, resolving the thermal property deficiency in conventional packages.
2Strength
If the main semiconductor chip is completely covered by molding layers, then protection is improved, but heat discharge capability deteriorates
Solution Approach 1:
The molding layer is designed with differentiated coverage: it protects the lateral surfaces of the semiconductor chip while deliberately exposing the top surface. This local quality differentiation allows the chip to receive mechanical protection where needed while maintaining heat discharge capability at the exposed top surface, resolving the contradiction between protection and thermal management.
3Adaptability or versatility
If multiple redistribution substrates are used with complex layering, then signal and power transmission are improved, but device complexity increases
Solution Approach 1:
The redistribution substrate is designed to perform multiple functions simultaneously: it provides signal redistribution, power delivery, and thermal conduction through its layered structure with conductive patterns and vias. This multi-functionality reduces the need for separate dedicated structures, thereby managing complexity while enhancing transmission capabilities.
Solution Approach 2:
The invention utilizes vertical layering with multiple redistribution substrates stacked at different levels, creating a three-dimensional arrangement that enables complex signal and power routing without increasing planar footprint. This dimensional approach allows high-density interconnection while maintaining manageable structural complexity through systematic layer design.
Data Source
AI summary
A semiconductor package comprising a main semiconductor chip having a first thickness, at least one semiconductor device on one side of the main semiconductor chip and having a second thickness less than the first thickness, a first molding layer that covers the main semiconductor chip and the semiconductor device so as to expose a top surface of the semiconductor device and to expose a top surface and a portion of a lateral surface of the main semiconductor chip, a first redistribution substrate below the first molding layer, a second redistribution substrate on the first molding layer, and a mold via that penetrates the first molding layer and connects the first redistribution substrate to the second redistribution substrate.