Semiconductor Package Heat Sink Bonding for Low-Stress Cooling

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Solution Overview

Problem

Existing semiconductor package structures face inefficiencies in heat dissipation due to thermal interface materials with low thermal conductivity, which can lead to thermal stress and warpage, and existing solutions do not adequately address these issues.

Innovation Solution

A semiconductor package structure that combines a thermal interface material with a bonding layer, spaced apart to prevent coefficient of thermal expansion mismatches, and optionally includes multiple heatsinks and notches or gaps in the thermal interface material to enhance heat dissipation efficiency and reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a thermal interface material is used between the semiconductor die and the heatsink, then heat transfer is facilitated, but the low thermal conductivity of the material causes thermal stress and warpage

Engineering Contradiction:
Improveheat transfer efficiencyVSAvoidthermal stress and warpage
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The thermal interface material is segmented into multiple discrete beads rather than a continuous layer. This segmentation allows each bead to independently accommodate thermal expansion differences, reducing overall thermal stress and warpage while maintaining effective heat transfer paths from the die to the heatsink

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The invention changes the physical state and distribution parameters of the thermal interface material from a continuous layer to discrete beads with specific size, spacing, and density parameters. This parameter change optimizes both thermal conductivity and stress distribution characteristics

Inventive Principle:
Principle #35Parameter changes

2Reliability

If a bonding layer is added to improve heat dissipation, then thermal conductivity improves, but the coefficient of thermal expansion mismatch causes reliability issues

Engineering Contradiction:
Improveheat dissipation efficiencyVSAvoidcoefficient of thermal expansion mismatch
Core Design Contradiction:
ReliabilityVSStability of the object's composition

Solution Approach 1:

The bonding layer acts as an intermediary between the semiconductor die and the thermal interface material beads. It provides mechanical support and thermal conduction while its specific material properties help bridge the coefficient of thermal expansion mismatch between the rigid die and the softer thermal interface material

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The invention uses a composite structure combining the bonding layer with discrete thermal interface material beads. This composite approach allows optimization of each layer's properties - the bonding layer for mechanical strength and thermal conduction, and the beads for stress accommodation and heat transfer

Inventive Principle:
Principle #40Composite materials

3Reliability

If thermal interface material is placed in contact with molding material, then heat dissipation path is extended, but gas entrapment during manufacturing reduces reliability

Engineering Contradiction:
Improveheat dissipation pathVSAvoidgas entrapment
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The thermal interface material is segmented into discrete beads with spacing between them, creating gaps that allow gas to escape during the molding process. This segmentation maintains effective heat transfer through the beads while eliminating gas entrapment issues associated with continuous material layers

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The discrete bead structure creates a porous or gap-filled configuration that allows gas permeability during manufacturing. The spaces between beads serve as gas escape pathways while the beads themselves maintain thermal conduction, solving both heat dissipation and gas entrapment concerns

Inventive Principle:
Principle #31Porous materials

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This combination improves heat-dissipation efficiency, reduces thermal stress, and enhances manufacturability and reliability, particularly in high-power applications, while preventing issues related to thermal expansion mismatches and gas release during manufacturing.

Implementation Method 1

A thermal interface material is interposed between the semiconductor die and the heatsink to facilitate heat transfer from the semiconductor die to the heatsink

Methodology Applied
Scientific EffectThermal conduction: Conduction (thermal)

Implementation Method 2

A heatsink is commonly used to transfer the heat away

Methodology Applied
Scientific EffectHeat dissipation: Heat Sink

Data Source

PatentEP3751603B1Semiconductor package with a heat sink bonded to a semiconductor chip with a bonding layer and to a molding material with a thermal interface material
Publication Date: 2024.10.09 MEDIATEK INC
  • EP3751603B1 patent drawingFigure 1~2
  • EP3751603B1 patent drawingFigure 3A~3B
  • EP3751603B1 patent drawingFigure 4

AI summary

A semiconductor package structure (200, 300, 400) includes a substrate (102), a semiconductor die (106), a molding material (108), a first bonding layer (126), and a thermal interface material (120). The semiconductor die (106) is disposed over the substrate (102). The molding material (108) surrounds the semiconductor die (106). The first bonding layer (126) is disposed over the semiconductor die (106). The thermal interface material (120) is disposed over the molding material (108). The semiconductor package structure (200, 300, 400) may further comprise a heatsink (122) disposed over the bonding layer (126), wherein the thermal interface material (120) may connect the molding material (108) and the heatsink (122). The inclusion of both of thermal interface material (120) and the bonding layer (126) improves the heat dissipation efficiency without increasing stress, which is preferred for high-power applications, resulting at the same time in enhancement of thermal performance, manufacturability and reliability. The thermal interface material (120) may be adhesive. The thermal interface material (120) may surround the first bonding layer (126). A metal layer (124) may be disposed between the first bonding layer (126) and the semiconductor die (106). The thermal interface material (120) may partially surround the metal layer (124) and the bonding layer (126). The thermal interface material (120) may be spaced apart from the metal layer (124) and the bonding layer (126) by a gap, to prevent the issues caused by different coefficients of thermal expansion (CTE) of the thermal interface material (120), the metal layer (124) and the bonding layer (126). The thermal interface material (120) may be thicker than the metal layer (124) and thicker than the bonding layer (126). The thermal interface material (120) may have a notch and/or may be cut off by a gap (132) or by a plurality of gaps, to release gas generated during the manufacturing process. The semiconductor package structure (200, 300, 400) may further comprise a conductive element (104) (e.g., conductive ball structures, conductive pillar structures or conductive paste structures) disposed between the semiconductor die (106) and the substrate (102). The semiconductor package structure (400) may further comprise another heatsink (130) disposed below the substrate (102) and bonded onto the substrate (102) through a second bonding layer (128), wherein the first bonding layer (126) has a melting point lower than the second bonding layer (128). The first bonding layer (126) may comprise SnBi, SnBiAg, or a combination thereof. A sidewall of the thermal interface material (120) may be aligned with a sidewall of the molding layer (108) or inside it. The upper surface of the semiconductor die (106) may be covered or exposed by the molding material (108).