Semiconductor Package Heat Sink Layout for Logic Chip Cooling
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Solution Overview
Problem
Heat generated from logic chips in system-in-package configurations is not efficiently dissipated, leading to performance degradation due to inadequate heat dissipation through the package substrate.
Innovation Solution
A semiconductor package design that includes a heat sink on top of the logic chip, electrically insulated from the package substrate, to rapidly dissipate heat, with the memory chip mounted on the heat sink and directly connected to the package substrate via conductive wires, allowing for independent heat management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the memory chip is mounted on the package substrate and the logic chip is mounted on the package substrate, then the system-in-package structure is formed, but heat generated from the logic chip cannot be rapidly dissipated
Solution Approach 1:
The patent segments the mounting structure by introducing a separate heat sink substrate that is electrically insulated from the package substrate. The memory chip is mounted on the heat sink substrate while the logic chip remains on the package substrate, creating distinct thermal and electrical pathways that enable independent heat management.
Solution Approach 2:
The heat sink substrate acts as an intermediary component between the logic chip and the heat dissipation path. It provides a dedicated thermal conduction path through its thermal conduction layer to dissipate heat from the logic chip without interfering with the electrical connections between the memory chip and package substrate.
2Reliability
If the memory chip is mounted on the package substrate, then electrical connection is achieved, but heat from logic chip accumulates and degrades performance
Solution Approach 1:
The patent divides the mounting function into two separate substrates: the package substrate for electrical connections and the heat sink substrate for thermal management. This segmentation allows the memory chip to maintain reliable electrical connections to the package substrate while the logic chip's heat is independently managed through the heat sink substrate.
Solution Approach 2:
The patent extracts the heat dissipation function from the package substrate by introducing a separate heat sink substrate with dedicated thermal conduction capabilities. This extraction allows the package substrate to focus on electrical connections while the heat sink substrate handles thermal management, preventing performance degradation.
3Temperature
If heat is dissipated through the package substrate, then thermal management is attempted, but the package substrate cannot rapidly dissipate heat
Solution Approach 1:
The heat sink substrate serves as an intermediary specialized component that mediates between the logic chip's heat generation and the external environment. Its thermal conduction layer is specifically designed for rapid heat dissipation, providing a dedicated thermal pathway that does not compromise the package substrate's electrical connection function.
Solution Approach 2:
The heat sink substrate provides multi-functionality by simultaneously serving as a mounting platform for the memory chip and a thermal conduction path for the logic chip. This multi-functional design enables effective heat dissipation without adding excessive manufacturing complexity, as a single component accomplishes multiple objectives.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively dissipates heat from the logic chip, preventing performance degradation and maintaining system efficiency by isolating the heat sink from the package substrate and directly connecting the memory chip to the substrate.
Implementation Method 1
a heat sink disposed on an upper surface of the logic chip and configured to dissipate a heat generating from the logic chip
Implementation Method 2
a conductive wire extending from the memory chip to the second signal pad
Data Source
AI summary
A semiconductor package includes a package substrate, a logic chip on an upper surface of the package substrate and electrically connected to the package substrate, a heat sink contacting an upper surface of the logic chip to dissipate a heat generating from the logic chip, and a memory chip disposed on an upper surface of the heat sink and electrically connected to the package substrate.