Semiconductor Package Structure With Backside Heat Spreader
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Solution Overview
Problem
Existing semiconductor packaging technologies face challenges in improving thermal and electrical performance while maintaining process efficiency, particularly in flip chip type packaging, which is limited by individual chip processing and lacks effective heat dissipation and electrical connectivity solutions.
Innovation Solution
A semiconductor package device incorporating a redistribution layer member, a molding layer that exposes the chip's backside, a thermal interface material member, and a heat spreading member, with conductive contact elements and through-holes for enhanced thermal and electrical connectivity, allowing for improved heat dissipation and electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If individual chip packaging is performed using existing flip chip type technology, then each chip can be packaged, but process efficiency is greatly reduced
Solution Approach 1:
The patent merges multiple individual chip packaging operations into a single batch processing step by stacking multiple chips on a carrier substrate simultaneously. The molding compound is applied to encapsulate multiple chips in one operation, and the carrier substrate is removed as a single unit, thereby dramatically improving process efficiency while reducing overall packaging process complexity
Solution Approach 2:
The packaging process is segmented into distinct stages: chip stacking on carrier substrate, molding compound application, and carrier substrate removal. This segmentation allows each stage to be optimized independently and enables parallel processing of multiple chips during the molding stage, resolving the efficiency bottleneck in traditional sequential packaging
2Reliability
If traditional packaging structures are used, then manufacturing is simpler, but thermal and electrical performance cannot be improved
Solution Approach 1:
The carrier substrate serves as an intermediary structure that enables both thermal management and electrical connectivity. It provides a platform for stacking chips with controlled thermal interfaces and electrical connections, allowing heat to be conducted away from the chips while maintaining electrical signal integrity, thus improving thermal and electrical performance without requiring complex individual packaging for each chip
Solution Approach 2:
The molding compound performs multiple functions simultaneously: it provides mechanical support and protection for the stacked chips, establishes thermal pathways for heat dissipation, and maintains electrical isolation between adjacent chips. This multi-functionality improves overall package performance while avoiding the need for separate dedicated structures for each function
3Reliability
If chips are stacked through TSV connection structures, then connectivity is improved, but thermal management issues arise
Solution Approach 1:
The patent nests multiple chips vertically on the carrier substrate, with each chip stacked above the previous one. This nested arrangement allows TSV connection structures to provide electrical connectivity between chips while the carrier substrate and molding compound collectively manage thermal pathways. The nested structure enables compact packaging while maintaining separate thermal and electrical pathways
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances thermal and electrical performance of semiconductor packages by facilitating efficient heat transfer and electrical connections, thereby improving manufacturing efficiency and productivity.
Implementation Method 1
a thermal interface material member disposed on the molding layer in contact with the backside of the at least one chip, and a heat spreading member disposed on the thermal interface material member
Implementation Method 2
a heat spreading member disposed on the thermal interface material member
Data Source
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AI summary
Disclosed are a semiconductor package device and a method of manufacturing the same. The semiconductor package device includes a redistribution layer member, at least one chip disposed on a first surface of the redistribution layer member, the at least one chip being electrically connected to the redistribution layer member, a molding layer disposed on the first surface of the redistribution layer member so as to at least partially expose a backside of the at least one chip while filling a space around the at least one chip, a thermal interface material member disposed on the molding layer in contact with the backside of the at least one chip, and a heat spreading member disposed on the thermal interface material member.