Multi-Chip Semiconductor Package with Segmented Signal and Heat Vias
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Solution Overview
Problem
Existing semiconductor packages face challenges with thermal stability and operational reliability due to the integration of multiple semiconductor chips, particularly in package-on-package configurations, which can lead to issues with wire layouts and thermal budgets.
Innovation Solution
A semiconductor package design featuring a first through via with a narrower width than a second through via, where the second via is electrically floated and serves as a heat transfer path, while the first via functions as a signal delivery path, along with a dummy wiring pattern to enhance thermal stability and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple semiconductor chips are integrated onto one package using package-on-package technique, then chip stacking density is improved, but wire layout problems and thermal budget issues occur
Solution Approach 1:
The patent divides the through via system into two distinct segments: signal through vias for electrical connectivity and heat transfer through vias for thermal management. This segmentation allows independent optimization of signal integrity and heat dissipation pathways, resolving the wire layout problems caused by integrated multi-function vias in package-on-package configurations.
Solution Approach 2:
The patent introduces an intermediary structure (the heat transfer through via) that mediates between the heat generating components and the heat dissipation path. This intermediary enables thermal budget management without interfering with signal wire layouts, thus improving both chip stacking density and wire layout reliability.
2Quantity of substance
If multiple semiconductor chips are integrated onto one package using package-on-package technique, then chip stacking density is improved, but thermal budget problems occur
Solution Approach 1:
The patent segments the thermal management function from signal transmission function by creating dedicated heat transfer through vias separate from signal through vias. This allows efficient heat dissipation pathways to be established without compromising signal integrity, enabling higher chip stacking density while maintaining thermal budget control.
Solution Approach 2:
The patent creates a copy of the through via structure with different dimensions and electrical properties - the heat transfer through via mirrors the signal through via structure but with larger diameter and different electrical connection characteristics, optimizing it specifically for thermal conduction while maintaining structural consistency.
3Device complexity
If through vias are used for both signal delivery and heat transfer, then device complexity is reduced, but electrical interference increases
Solution Approach 1:
The patent segments the via functions into distinct signal through vias and heat transfer through vias, eliminating electrical interference between signal and thermal pathways. Although this increases structural complexity slightly, it dramatically improves electrical reliability by preventing cross-talk and interference in high-density package-on-package configurations.
Solution Approach 2:
The patent applies different local qualities to different via types: signal through vias maintain electrical conductivity for signal delivery, while heat transfer through vias are optimized for thermal conduction with appropriate electrical isolation. This local differentiation resolves electrical interference issues while maintaining overall device functionality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design improves thermal stability and operational reliability by efficiently dissipating heat through a wider heat transfer via and reducing electrical interference, thereby enhancing the performance of multi-chip semiconductor packages.
Implementation Method 1
a second through via on a fourth region, adjacent to the third region, of the second substrate and directly connecting the second substrate to the heat radiator
Implementation Method 2
a first through via disposed on a second region, adjacent to the first region, of the first substrate and directly connecting the first substrate to the second substrate
Data Source
AI summary
A semiconductor package includes a package substrate, a first semiconductor chip mounted on the package substrate, a first molding layer on the package substrate and surrounding the first semiconductor chip, a redistribution layer on the first molding layer, a first through via that vertically penetrates the first molding layer and connects the package substrate to the redistribution layer, a second semiconductor chip mounted on the redistribution layer, a second molding layer on the redistribution layer and surrounding the second semiconductor chip, and a second through via that vertically penetrates the second molding layer and is connected to the redistribution layer. A first width of the first through via is less than a second width of the second through via. The second through via is electrically floated from a signal circuit of the second semiconductor chip.