Semiconductor Package Structure for Die Height Compensation

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Solution Overview

Problem

In semiconductor packaging, the integration of semiconductor dies with varying heights leads to reliability issues such as cracks in the molding compound and redistribution layer due to grinding and planarization processes, which can result in reduced package reliability.

Innovation Solution

The use of conductive bumps and pillars to compensate for die height variations, reducing the need for extensive molding and grinding, and improving the reliability of the package structure by maintaining a low pitch for heterogeneous bonding.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If grinding and planarization processes are used to integrate semiconductor dies with varying heights, then integration is achieved, but cracks occur in the molding compound and redistribution layer reducing reliability

Engineering Contradiction:
Improveintegration of semiconductor dies with varying heightsVSAvoidpackage reliability
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent applies preliminary action by forming compensation structures (such as molding compound additions or pillars) on the semiconductor dies before the final packaging process. These structures pre-compensate for height variations, eliminating the need for subsequent grinding and planarization that would cause cracks. The compensation structures are created in advance to match the required height profile, preventing reliability issues before they occur.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent converts the harmful effect of height variations into a benefit by using the variation itself as a design parameter. Instead of treating height differences as a problem to be eliminated through damaging grinding processes, the invention utilizes these variations by adding compensation structures that leverage the existing height differences to achieve proper alignment and connection, thereby improving rather than reducing reliability.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

2Adaptability or versatility

If extensive molding and grinding are performed to accommodate die height variations, then integration is achieved, but the reliability window is reduced

Engineering Contradiction:
Improveintegration capabilityVSAvoidreliability window
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent performs the compensation action preliminarily by forming height-adjustment structures during the initial packaging stages. Molding compound is added or pillars are formed to compensate for height variations before final encapsulation and testing. This preliminary compensation eliminates the need for post-processing grinding that would reduce the reliability window, as all necessary adjustments are made while the structures are more accessible and less constrained.

Inventive Principle:
Principle #10Preliminary action

3Ease of manufacture

If die height variations are not compensated, then manufacturing is simpler, but cracks occur in the molding compound and redistribution layer

Engineering Contradiction:
Improvemanufacturing simplicityVSAvoidcrack resistance
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent applies self-service by having the semiconductor dies themselves participate in the height compensation process. Compensation structures are formed directly on the die surfaces using materials and processes that are already part of the standard manufacturing flow. The dies essentially service their own height variation needs through in-situ formation of compensation structures, eliminating the need for separate, complex external compensation processes while maintaining crack resistance.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS12051652B2Package structure and method of fabricating the same
Publication Date: 2024.07.30 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12051652B2 patent drawing
  • US12051652B2 patent drawing
  • US12051652B2 patent drawing

AI summary

A package structure includes a plurality of semiconductor dies, an insulating encapsulant, a redistribution layer and a plurality of connecting elements. The insulating encapsulant is encapsulating the plurality of semiconductor dies. The redistribution layer is disposed on the insulating encapsulant in a build-up direction and electrically connected to the plurality of semiconductor dies, wherein the redistribution layer includes a plurality of conductive lines, a plurality of conductive vias and a plurality of dielectric layers alternately stacked, and a lateral dimension of the plurality of conductive vias increases along the build-up direction. The connecting elements are disposed in between the redistribution layer and the semiconductor dies, wherein the connecting elements includes a body portion joined with the semiconductor dies and a via portion joined with the redistribution layer, wherein a lateral dimension of the via portion decreases along the build-up direction.