Semiconductor Package Height Compensation Without Spacer Chips
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Solution Overview
Problem
The high costs and decreased productivity associated with manufacturing multi-chip packages due to the use of spacer chips in supporting overhanging semiconductor chips, which require processes like die attach and sawing.
Innovation Solution
A semiconductor package design that includes first and second semiconductor chips of different heights with a support structure on the second chip to compensate for height differences, allowing third chips to be stacked and supported without the need for a conventional spacer chip, formed during the wiring bonding process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If a spacer chip is used to support an overhanging portion of the uppermost semiconductor chip, then the chip structure stability is improved, but the manufacturing cost increases and productivity decreases due to additional processes like back lap, sawing, and die attach
Solution Approach 1:
The invention extracts and eliminates the spacer chip component from the multi-chip package structure. Instead of using a separate spacer chip to support the overhanging portion, the patent uses the interconnection structure itself (solder bumps and underfill material) to provide the necessary support, thereby removing the need for additional spacer chip manufacturing processes
Solution Approach 2:
The invention merges the support function with the interconnection structure. The solder bumps and underfill material that are already present for electrical connection also serve to support the overhanging chip portion, combining multiple functions into a single integrated structure rather than requiring separate support components
2Stability of the object's composition
If a spacer chip is used to support an overhanging portion of the uppermost semiconductor chip, then the chip structure stability is improved, but the manufacturing cost increases due to additional processes like back lap, sawing, and die attach
Solution Approach 1:
The invention extracts and eliminates the spacer chip component from the multi-chip package structure. Instead of using a separate spacer chip to support the overhanging portion, the patent uses the interconnection structure itself (solder bumps and underfill material) to provide the necessary support, thereby removing the need for additional spacer chip manufacturing processes
Solution Approach 2:
The invention merges the support function with the interconnection structure. The solder bumps and underfill material that are already present for electrical connection also serve to support the overhanging chip portion, combining multiple functions into a single integrated structure rather than requiring separate support components
3Productivity
If multiple semiconductor chips with different heights are stacked, then the productivity and cost efficiency are improved by eliminating spacer chips, but the alignment and support of higher chips become more difficult
Solution Approach 1:
The invention introduces underfill material as an intermediary substance between the chips of different heights. This underfill material fills the gaps and provides a supportive matrix that maintains alignment and prevents shifting of the overhanging chip portions, enabling precise stacking without requiring additional alignment mechanisms
Solution Approach 2:
The invention applies underfill material in advance during the stacking process to create a stable foundation before final positioning. The underfill is applied to the lower chips first, creating a prepared surface that guides and maintains the alignment of subsequently stacked chips, preventing misalignment issues
Data Source
AI summary
A semiconductor package includes a package substrate, at least one first semiconductor chip on the package substrate and having a first height as measured from the package substrate, at least one second semiconductor chip on the package substrate spaced apart from the first semiconductor chip and having a second height less than the first height as measured from the package substrate, at least one third semiconductor chip stacked on the first and second semiconductor chips, and at least one support structure between the at least one second semiconductor chip and the at least one third semiconductor chip configured to support the at least one third semiconductor chip.


