Semiconductor Package Height Reduction via Thermo-Compression Bonding
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Solution Overview
Problem
Conventional semiconductor device packaging techniques are expensive and require additional equipment and processing steps, while also being inefficient in reducing package height and increasing bandwidth for electrical connections.
Innovation Solution
A modified chip-on-wafer technique combined with a modified fan-out-packaging method that uses thermo-compression bonding and through vias to minimize package height and enhance electrical connectivity, allowing for finer pitches and reduced risk of shorting.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If conventional packaging techniques are used, then manufacturing simplicity is maintained, but package height is excessive and bandwidth is insufficient
Solution Approach 1:
The patent transitions from planar 2D packaging to 3D vertical stacking architecture, where multiple semiconductor dice are stacked vertically on a substrate. This dimensional change enables reduced package height footprint while increasing bandwidth through multiple stacked layers, resolving the contradiction between compact size and processing complexity
Solution Approach 2:
The patent implements nested structures where semiconductor dice are stacked within a compact package housing, with each die nested vertically above the previous one. This nesting approach maximizes space utilization, reducing overall package height while maintaining multiple functional layers without requiring additional processing steps
2Ease of manufacture
If solder bumps are used for electrical connections, then ease of manufacture is maintained, but package height increases and bandwidth is reduced
Solution Approach 1:
The patent extracts and eliminates the solder bump layer from the electrical connection architecture, replacing it with direct copper-to-copper bonding through thermo-compression. This removal of the intermediate solder layer reduces package height while maintaining manufacturing feasibility through advanced bonding techniques
Solution Approach 2:
The patent substitutes the mechanical solder bump connection system with a direct thermal-compression bonding system. This replacement eliminates the need for solder reflow processes and large solder bumps, achieving reduced package height while maintaining ease of manufacture through controlled compression and heating
3Reliability
If fan-out-packaging techniques are used, then bandwidth is increased, but manufacturing cost increases and additional equipment is required
Solution Approach 1:
The patent creates a multi-functional substrate that simultaneously provides mechanical support, electrical interconnection, and thermal management capabilities. This universal substrate design achieves enhanced electrical connectivity through integrated through-vias and copper traces while avoiding the need for separate fan-out packaging equipment and processes
Solution Approach 2:
The patent merges multiple functions into a single integrated substrate structure, combining support, electrical interconnection, and signal routing functions. This consolidation achieves improved electrical connectivity through through-vias and copper traces while reducing manufacturing cost by eliminating the need for separate fan-out packaging processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach results in reduced package height, increased bandwidth, and cost-effective production with fewer processing steps, while minimizing the risk of electrical shorting and potential component damage.
Implementation Method 1
thermo-compression bonding
Data Source
AI summary
Semiconductor device packages may include a support structure having electrical connections therein. Semiconductor device modules may be located on a surface of the support structure. A molding material may at least partially surround each semiconductor module on the surface of the support structure. A thermal management device may be operatively connected to the semiconductor device modules on a side of the semiconductor device modules opposite the support structure. At least some of the semiconductor device modules may include a stack of semiconductor dice, at least two semiconductor dice in the stack being secured to one another by diffusion of electrically conductive material of electrically conductive elements into one another.