Semiconductor Package Layout for Low-Resistance Horizontal Die Stacking

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Solution Overview

Problem

Conventional semiconductor packages with vertically stacked dies experience increased die-to-die resistance as the number of dies in a die stack increases, due to the inability to directly electrically connect non-adjacent dies.

Innovation Solution

The semiconductor package includes a die stack with vertically aligned and horizontally stacked dies that are directly electrically connected through a second die, reducing die-to-die resistance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the number of dies in a die stack is increased to improve integration density, then integration density is improved, but die-to-die resistance increases due to inability to directly electrically connect non-adjacent dies

Engineering Contradiction:

Improveintegration densityVSAvoiddie-to-die resistance

Core Design Contradiction:

Quantity of substanceVSReliability

Solution Approach 1:

The patent transitions from a conventional vertical stacking approach to a horizontal stacking approach where dies are arranged side-by-side in the same plane. This dimensional change allows non-adjacent dies to be directly electrically connected through the interconnect structure, eliminating the resistance issue while maintaining high integration density through increased die count in the horizontal arrangement.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent inverts the conventional vertical stacking paradigm by implementing horizontal stacking. Instead of stacking dies vertically one on top of another, the dies are positioned horizontally adjacent to each other, fundamentally changing the stacking direction and enabling direct electrical connections between non-adjacent dies through the interconnect structure.

Inventive Principle:

Principle #13The other way round (Inversion)

2Area of stationary object

If vertically stacked dies are used to reduce package area, then package area is reduced, but die-to-die resistance increases with more dies

Engineering Contradiction:

Improvepackage areaVSAvoiddie-to-die resistance

Core Design Contradiction:

Area of stationary objectVSReliability

Solution Approach 1:

The patent changes the stacking dimension from vertical to horizontal, arranging dies side-by-side rather than one above another. This dimensional transformation reduces package area through compact horizontal arrangement while enabling direct electrical connections between non-adjacent dies, thereby maintaining low die-to-die resistance even as die count increases.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent inverts the conventional vertical stacking approach by implementing horizontal stacking. This inversion allows non-adjacent dies to be directly electrically connected through the interconnect structure, resolving the resistance issue while achieving compact package area through efficient horizontal die arrangement.

Inventive Principle:

Principle #13The other way round (Inversion)

Data Source

PatentUS12230613B2Vertical semiconductor package including horizontally stacked dies and methods of forming the same

Publication Date: 2025.02.18 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A semiconductor package includes a first connection die including a semiconductor substrate and an interconnect structure, and a first die stack disposed on the first connection die and including stacked dies, each of the stacked dies including a semiconductor substrate and an interconnect structure including a first connection line that is electrically connected to the interconnect structure of the first connection die. An angle formed between a plane of the first connection die and a plane of each stacked die ranges from about 45° to about 90°.