Semiconductor Package Layout for Closely Spaced Image Sensors
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Solution Overview
Problem
As the number of image sensors in a semiconductor package increases, interconnection paths become complicated and lengthened, and mounting space is limited, necessitating new semiconductor package structures to improve electrical efficiency and reliability.
Innovation Solution
A semiconductor package design that includes a package substrate with a connection substrate featuring a support layer, through-electrodes, and a redistribution layer, allowing for the close placement of image sensor chips and other semiconductor chips, reducing the mounting area while maintaining electrical connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of image sensors in a semiconductor package increases, then the functionality and imaging capability are improved, but the interconnection paths become complicated and lengthened, and the mounting space is limited
Solution Approach 1:
The patent transitions from a conventional planar mounting arrangement to a three-dimensional stacked architecture where image sensor chips are vertically positioned above the package substrate. This vertical stacking enables multiple image sensors to be integrated within a compact footprint, reducing the mounting area while minimizing interconnection path length through direct vertical coupling rather than lateral routing.
Solution Approach 2:
The patent implements a nested structure where image sensor chips are positioned within the vertical profile of the package, with each chip stacked above the previous one. This nesting approach allows multiple sensors to occupy overlapping horizontal space at different vertical levels, effectively reducing the overall mounting footprint and simplifying interconnections by eliminating the need for extensive lateral routing between sensors.
2Adaptability or versatility
If the number of image sensors in a semiconductor package increases, then the functionality and imaging capability are improved, but the mounting space is limited
Solution Approach 1:
The patent utilizes the vertical dimension by stacking image sensor chips above the package substrate in multiple layers. This three-dimensional arrangement allows multiple sensors to be integrated within a small horizontal footprint, effectively reducing the mounting area while maintaining the ability to incorporate multiple sensors for enhanced imaging functionality.
Solution Approach 2:
The patent employs a nested stacking configuration where image sensor chips are vertically arranged one above another within the package structure. This nesting enables multiple sensors to share the same horizontal space at different vertical levels, significantly reducing the overall mounting area required compared to a planar side-by-side arrangement.
3Area of stationary object
If image sensor chips are placed closer together, then the mounting area is reduced, but the electrical connectivity and signal integrity may be affected
Solution Approach 1:
The patent resolves the conflict between close spacing and electrical connectivity by moving the interconnection path into the vertical dimension. Through-electrodes penetrate the package substrate vertically to establish electrical connections with the stacked image sensor chips, enabling reliable signal transmission despite the reduced horizontal spacing between chips.
Solution Approach 2:
The patent introduces through-electrodes as intermediary connection elements that penetrate the package substrate to establish reliable electrical pathways between the stacked image sensor chips. These through-electrodes act as mediators that maintain signal integrity and electrical connectivity even when chips are positioned in close vertical proximity, overcoming the challenges of dense packing.
Data Source
AI summary
A semiconductor package includes a package substrate, a connection substrate on the package substrate, a first image sensor chip on the connection substrate, a second image sensor chip on the connection substrate, the second image sensor chip being horizontally spaced apart from the first image sensor chip, and a memory chip disposed on the package substrate and electrically connected to the first image sensor chip through the connection substrate. A distance between the first image sensor chip and the second image sensor chip is less than a thickness of the first image sensor chip.