Stacked Semiconductor Package Heat Dissipation via Inactive Surface Protrusions
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor packages face challenges in achieving high integration, high speed, and efficient heat radiation while maintaining a compact form factor, particularly in vertically stacked configurations.
Innovation Solution
A semiconductor package design featuring a first semiconductor package with a package substrate, a semiconductor chip, connection pads, bonding wires, and a molding layer, along with a second semiconductor package stacked on top, connected via connection terminals on the inactive surface of the first chip, allowing for increased thickness and improved heat radiation without widening the package.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If vertically stacked configuration is used to increase integration, then high integration is achieved, but heat radiation becomes more difficult
Solution Approach 1:
The patent transitions from planar heat dissipation to three-dimensional heat radiation by forming protrusions on the inactive surface that extend upward between stacked packages. This vertical dimension allows heat to radiate in multiple directions (upward, downward, and laterally) rather than being confined to a single plane, effectively solving the heat radiation problem in vertically stacked configurations.
Solution Approach 2:
The inactive surface is segmented into multiple protrusions rather than being a flat continuous surface. Each protrusion acts as an independent heat radiation element, increasing the total surface area available for heat dissipation. This segmentation allows heat to escape through multiple distributed pathways rather than relying on a single heat dissipation route.
2Reliability
If connection terminals are added to inactive surface to increase signal terminals, then electrical characteristics are improved, but package width must be increased
Solution Approach 1:
The patent utilizes the vertical dimension by forming protrusions that extend upward from the inactive surface. Connection terminals are placed on these protrusions, allowing additional signal terminals to be added without increasing the horizontal footprint. This transforms a two-dimensional plane problem into a three-dimensional space solution, enabling more connection terminals within the same package width.
3Reliability
If molding layer covers side surfaces of semiconductor chip, then protection is improved, but connection terminals cannot be placed on inactive surface
Solution Approach 1:
The molding layer is segmented to cover only specific regions (side surfaces of the semiconductor chip) while deliberately leaving the protrusions on the inactive surface exposed. This selective coverage maintains protection where needed while preserving the adaptability required for placing connection terminals on the protrusions, resolving the conflict between protection and versatility.
Solution Approach 2:
The molding layer provides localized protection only where required (side surfaces) rather than uniformly covering the entire chip. This local quality approach allows different regions to have different functions: covered regions provide protection while exposed protrusions provide terminal placement capability, simultaneously achieving both protection and adaptability.
Data Source
AI summary
A semiconductor package includes a first semiconductor package, a second semiconductor package on the first semiconductor package, and a plurality of connection terminals between the first semiconductor package and the second semiconductor package. The first semiconductor package may include a package substrate, a semiconductor chip on the package substrate and having a first surface and a second surface facing each other, the first surface being adjacent to the second semiconductor package, a plurality of connection pads between the first surface of the semiconductor chip and the connection terminals, and a molding layer on the package substrate and covering side surfaces of the semiconductor chip, the molding layer being spaced apart from the connection terminals.