Semiconductor Package Structure With Inactive Vias for Vertical Routing
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Solution Overview
Problem
Semiconductor electronic devices face challenges in scaling down while maintaining electrical characteristics, quality, cost, and yield, as single semiconductor chips struggle to meet multifunctional and high-volume data processing needs.
Innovation Solution
A package structure incorporating at least one semiconductor device and at least one inactive element, with an encapsulant encapsulating both, and a redistribution structure providing a vertical conduction path between an upper electronic device and a substrate, bypassing the need for vertical conduction paths in the semiconductor device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple semiconductor chips are integrated to meet multifunctional needs, then functional capability is improved, but device complexity increases
Solution Approach 1:
The patent divides the package structure into distinct functional segments: active semiconductor devices for computation, inactive elements for signal routing, and encapsulant for protection. This segmentation allows each component to have a specialized function, achieving multifunctionality while maintaining manageable complexity through modular design
Solution Approach 2:
The inactive elements serve multiple functions: they provide vertical conduction paths for electrical signals, act as structural support pillars, and enable routing between different chip layers. This multi-functionality reduces the need for separate dedicated components, thereby reducing overall device complexity while maintaining versatility
2Reliability
If vertical conduction paths are implemented within semiconductor devices, then electrical connectivity is improved, but manufacturing difficulty increases
Solution Approach 1:
The patent extracts the vertical conduction path function from the active semiconductor devices and relocates it to separate inactive elements. This extraction allows the semiconductor devices to focus on their primary computational function while the inactive elements handle signal routing, simplifying the manufacturing process for both components and improving overall electrical connectivity
Solution Approach 2:
The inactive elements act as intermediary structures that facilitate vertical conduction between different chip layers without requiring complex through-silicon vias or other difficult-to-manufacture vertical connections within the active semiconductor devices themselves. These intermediary elements simplify the manufacturing process while maintaining reliable electrical connectivity
3Area of moving object
If semiconductor device dimensions are reduced for scaling, then integration density is improved, but electrical characteristics deteriorate
Solution Approach 1:
The patent transitions from planar two-dimensional integration to three-dimensional stacking architecture. By arranging semiconductor chips and inactive elements in vertical layers connected through vertical conduction paths, the design achieves higher integration density without further reducing the lateral dimensions of individual devices, thereby maintaining their electrical characteristics while increasing overall integration
Data Source
AI summary
A package structure, an assembly structure and a manufacturing method are provided. The package structure includes at least one semiconductor device, at least one inactive element and an encapsulant. The at least one inactive element is disposed around the at least one semiconductor device, and includes a main portion and at least one through via extending through the main portion. The encapsulant encapsulates the at least one semiconductor device and the at least one inactive element. A first surface of the encapsulant is substantially coplanar with a first surface of the at least one inactive element and a first surface of the at least one semiconductor device. A second surface of the encapsulant is substantially coplanar with a second surface of the at least one inactive element and a second surface of the at least one semiconductor device.