Semiconductor Package Integrating Passive Inductor on Die Backside
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Solution Overview
Problem
The existing semiconductor packages occupy a significant amount of space due to external passive components, and longer interconnection pathways lead to performance detriments in applications like smartphones, where space is limited and interconnection parasitics are detrimental.
Innovation Solution
A semiconductor package design that integrates a passive electrical component, such as an inductor, between the semiconductor die and the leadframe, with the component sandwiched between magnetic elements and connected via solder balls, reducing the footprint and improving electrical properties by reducing loop inductance and resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If passive electrical components are mounted externally on PCB, then ease of manufacture is improved, but device area increases and interconnection parasitics worsen
Solution Approach 1:
The patent merges the semiconductor die and passive electrical component into a single integrated package. The passive component is mounted on the back surface of the semiconductor die, combining two previously separate components (IC and passive component) into one unified structure, thereby reducing the overall device area while maintaining manufacturability through established packaging processes.
Solution Approach 2:
The patent utilizes the third dimension (vertical stacking) by mounting the passive electrical component on the back surface of the semiconductor die. This vertical integration approach transitions from a planar layout to a three-dimensional stacked architecture, effectively reducing the footprint area while accommodating multiple components within a compact volume.
2Ease of manufacture
If passive electrical components are mounted externally on PCB, then ease of manufacture is improved, but interconnection parasitics worsen
Solution Approach 1:
By integrating the passive electrical component directly onto the semiconductor die within the same package, the patent eliminates the external PCB interconnection pathway. This merging of components reduces the length of interconnection traces and minimizes parasitic inductance, capacitance, and resistance associated with external routing, thereby improving electrical performance while maintaining ease of manufacture through standard packaging techniques.
3Ease of manufacture
If semiconductor package and external passive components are used separately, then ease of manufacture is improved, but volume increases
Solution Approach 1:
The patent combines the semiconductor die and passive electrical component into a single integrated package structure. By mounting the passive component on the back surface of the die and encapsulating both within a single mold compound housing, the patent reduces the total volume occupied by these components compared to using them as separate discrete parts on a PCB.
Solution Approach 2:
The patent implements a nested arrangement where the passive electrical component is positioned on the back surface of the semiconductor die, and both components are enclosed within a single package housing. This nesting configuration allows the passive component to occupy space that would otherwise be unused, effectively utilizing the vertical dimension and reducing the overall volume footprint.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces the overall footprint and enhances electrical performance by integrating passive components within the package, minimizing the impact of interconnection parasitics and optimizing space usage in compact devices.
Implementation Method 1
forming a first magnetic material on a first surface of a conductive loop and forming a second magnetic material on a second surface of the conductive loop opposite the first surface to form an inductor
Data Source
AI summary
A semiconductor package includes a leadframe comprising input/output pins accessible external to the semiconductor package and a semiconductor die electrically connected to the leadframe. The semiconductor package also includes a passive electrical component mounted on a side of the semiconductor die opposite the leadframe. Mold compound encapsulates the passive electrical component, semiconductor die, and leadframe to form the semiconductor package. Associated methods are disclosed as well.