Semiconductor Package Inductor Integration
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Solution Overview
Problem
Conventional flip chip package fabrication processes increase costs and reduce throughput by adding metal layers to improve the quality factor (Q factor) of inductors, which is not efficient.
Innovation Solution
A semiconductor package design that integrates a passive device, such as an inductor, with a conductive pillar between a metal pad and a conductive bump, allowing the passive device to be thicker than conventional designs without additional metal layers, thereby reducing resistance and increasing the Q factor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional metal layers are added to improve the quality factor of inductors, then the quality factor increases, but fabrication costs increase and fabrication throughput decreases
Solution Approach 1:
The patent combines the inductor structure with the existing interconnection structure by integrating the inductor into the passive device layer rather than adding separate metal layers. This merging approach achieves the desired quality factor improvement without increasing fabrication complexity or reducing throughput, as the inductor is formed as part of the standard multi-layer fabrication process.
Solution Approach 2:
The patent transitions from improving inductor quality factor through additional horizontal metal layers to achieving it through vertical integration within the passive device layer. By utilizing the thickness dimension of the passive device layer and forming the inductor within this existing layer structure, the solution avoids adding more fabrication steps while still achieving the required electrical performance.
2Reliability
If additional metal layers are added to improve the quality factor of inductors, then the quality factor increases, but fabrication costs increase
Solution Approach 1:
The patent merges the inductor fabrication with the existing interconnection structure fabrication process. The inductor is formed within the passive device layer using the same fabrication steps already required for creating the multi-layer interconnection structure, eliminating the need for additional metal deposition and patterning steps that would increase manufacturing costs.
Solution Approach 2:
The passive device layer serves multiple functions: it provides the interconnection structure required for signal routing and simultaneously serves as the medium for forming the inductor. This multi-functionality approach allows the same layer to fulfill both roles without requiring separate dedicated layers, thereby reducing overall fabrication complexity and cost.
3Reliability
If the passive device is made thicker to reduce resistance, then the quality factor increases, but the device complexity increases
Solution Approach 1:
The patent utilizes the vertical thickness dimension of the passive device layer to achieve the desired electrical performance. By increasing the thickness of the passive device layer and forming the inductor within this enhanced thickness, the solution reduces resistance and improves quality factor without adding horizontal complexity or requiring additional layered structures.
Data Source
AI summary
A semiconductor package includes a substrate, a first passivation layer disposed on the substrate, and an under bump metallurgy layer disposed on the first passivation layer. An additional under bump metallurgy layer is disposed on the first passivation layer, isolated from the under bump metallurgy layer; and a conductive pillar disposed on the additional under bump metallurgy layer.