Stacked Semiconductor Package Using In-FAB Chip Redistribution
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Solution Overview
Problem
Current semiconductor packages face challenges in achieving high electrical performance and compact size due to limitations in redistribution substrate formation and heat-related performance deterioration during high-temperature processes.
Innovation Solution
A semiconductor package design featuring a redistribution substrate with sequentially stacked dielectric layers and redistribution patterns, where the second semiconductor chip is stacked vertically over the first chip, with conductive pillars connecting them, and the redistribution layer formed through an In-FAB process to improve electrical properties and reduce package size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If a conventional semiconductor package structure with separate redistribution substrates is used, then electrical connectivity is achieved, but package size increases and fabrication complexity increases
Solution Approach 1:
The patent combines the redistribution substrate function directly into the semiconductor chip structure by forming redistribution patterns on the chip surface. This integration eliminates the need for separate redistribution substrates, thereby reducing package size and simplifying fabrication processes while maintaining electrical connectivity functionality.
Solution Approach 2:
The semiconductor chip is designed to perform multiple functions: it serves as both the active device substrate and the redistribution substrate. The chip structure universally handles both signal processing and electrical redistribution, eliminating the need for dedicated redistribution layers and reducing overall package complexity.
2Reliability
If high-temperature processes are used during fabrication, then material bonding is achieved, but electrical performance deteriorates due to heat
Solution Approach 1:
The patent performs preliminary actions by forming all redistribution patterns and conductive structures on the semiconductor chip before final packaging. This allows electrical connections to be established at lower temperatures during chip fabrication, avoiding high-temperature damage to sensitive electrical components while ensuring material bonding is achieved in advance through controlled low-temperature processes.
Data Source
AI summary
A semiconductor package includes a redistribution substrate having first and second surfaces, a first semiconductor chip on the first surface, external terminals on the second surface, a second semiconductor chip above the first semiconductor chip, external connection members below the second semiconductor chip, conductive pillars electrically connecting the external connection members to the redistribution substrate. The second semiconductor chip includes a device layer, a wiring layer, and a redistribution layer on a semiconductor substrate. The wiring layer includes intermetallic dielectric layers, wiring lines, and a conductive pad connected to an uppermost wiring line. The redistribution layer includes a first redistribution dielectric layer, a first redistribution pattern, and a second redistribution dielectric layer. A vertical distance between the semiconductor substrate and the conductive pillars is less than that between the first semiconductor chip and the external terminals.