Semiconductor Package Inorganic Cap Layer for Heat and Impact Resistance

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing semiconductor packages face challenges in achieving increased reliability, durability, and efficient thermal management due to limitations in the materials and structures used.

Innovation Solution

A semiconductor package is designed with a buffer die and multiple memory dies stacked on it, covered by a mold layer and an inorganic layer (such as SiO2) that enhances thermal conductivity and stiffness, while being coplanar with the memory dies to improve structural integrity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If a mold layer is used to cover the semiconductor dies, then the package structure is simplified and manufacturing is easier, but the thermal conductivity and stiffness are insufficient for effective thermal management and structural integrity

Engineering Contradiction:
Improvepackage structureVSAvoidthermal management
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent applies composite materials by combining the mold layer with an inorganic layer (such as silicon oxide or silicon nitride) to create a layered structure. The mold layer provides ease of manufacture and coverage, while the inorganic layer contributes high thermal conductivity and stiffness. This composite approach resolves the contradiction by integrating materials with complementary properties, achieving both manufacturing simplicity and effective thermal management.

Inventive Principle:
Principle #40Composite materials

Solution Approach 2:

The inorganic layer is selectively applied only on specific regions of the mold layer, particularly in areas requiring enhanced thermal conductivity and stiffness. This local quality approach allows the package to maintain ease of manufacture with the mold layer while providing targeted thermal management and structural support where needed, resolving the contradiction between manufacturing simplicity and thermal reliability.

Inventive Principle:
Principle #3Local quality

2Ease of manufacture

If a mold layer is used to cover the semiconductor dies, then the package structure is simplified and manufacturing is easier, but the resistance to external impacts is insufficient

Engineering Contradiction:
Improvepackage structureVSAvoidexternal impacts
Core Design Contradiction:
Ease of manufactureVSObject-affected harmful factors

Solution Approach 1:

The patent uses composite materials by layering an inorganic material over the mold layer. The mold layer provides manufacturing simplicity and coverage, while the inorganic layer adds mechanical strength and resistance to external impacts. This composite structure resolves the contradiction by combining materials with different mechanical properties, achieving both ease of manufacture and impact resistance.

Inventive Principle:
Principle #40Composite materials

Solution Approach 2:

The inorganic layer acts as a protective barrier that beforehand cushions and absorbs external impacts before they reach the vulnerable semiconductor dies. This prior protection mechanism allows the package to maintain a simple mold layer structure for ease of manufacture while simultaneously providing enhanced resistance to external harmful factors.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

3Reliability

If the inorganic layer thickness is increased to improve thermal conductivity, then thermal management improves, but the manufacturing precision and coplanarity become more difficult to achieve

Engineering Contradiction:
Improvethermal managementVSAvoidcoplanarity
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent optimizes the thickness parameter of the inorganic layer to a specific range (about 2 μm to about 10 μm) that balances thermal conductivity improvement with manufacturing precision. By carefully controlling this parameter, the package achieves effective thermal management while maintaining coplanarity between the inorganic layer and the uppermost memory die top surface, resolving the contradiction between thermal performance and manufacturing precision.

Inventive Principle:
Principle #35Parameter changes

4Reliability

If the inorganic layer is made stiffer to improve structural integrity, then durability increases, but the manufacturing complexity and process difficulty increase

Engineering Contradiction:
ImprovedurabilityVSAvoidlayer structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent employs composite materials by combining the mold layer with an inorganic layer to achieve the desired stiffness and structural integrity. Rather than making the entire structure more complex, the inorganic layer is applied as a distinct functional layer with specific mechanical properties. This approach increases durability through the stiff inorganic layer while keeping the overall manufacturing process manageable by maintaining a clear layered structure.

Inventive Principle:
Principle #40Composite materials

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The proposed solution effectively enhances the thermal radiation efficiency, protects against external impacts, and increases the durability of the semiconductor package by utilizing an inorganic layer with higher thermal conductivity and stiffness than the mold layer.

Implementation Method 1

a thermal conductivity of the inorganic layer is greater than a thermal conductivity of the mold layer

Methodology Applied
Scientific EffectThermal conduction: Conduction (thermal)

Data Source

PatentUS20250029955A1Semiconductor package having an inorganic layer on a mold layer and method of fabricating the same
Publication Date: 2025.01.23 SAMSUNG ELECTRONICS CO LTD
  • US20250029955A1 patent drawing
  • US20250029955A1 patent drawing
  • US20250029955A1 patent drawing

AI summary

A semiconductor package includes: a buffer die; a plurality of memory dies stacked on the buffer die; a mold layer covering a portion of a top surface of the buffer die and lateral surfaces of the plurality of memory dies; and an inorganic layer disposed on the mold layer, wherein the inorganic layer covers at least a portion of the lateral surface of an uppermost memory die of the plurality of memory dies, wherein a top surface of the inorganic layer is substantially coplanar with a top surface of the uppermost memory die of the plurality of memory dies, and wherein the inorganic layer includes oxide or nitride.