Semiconductor Package Insulating Base Body Design
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Solution Overview
Problem
Conventional semiconductor packages face issues with thermal expansion mismatch between semiconductor chips and packaging substrates, leading to delamination, warpage, and increased fabrication costs due to the use of silicon interposers, which also result in low yield and high production costs.
Innovation Solution
A semiconductor package design that eliminates the need for a silicon interposer by using an insulating base body with a dielectric layer and a circuit layer, where the electronic element is bonded to the insulating base body through a bonding layer, and the circuit layer is electrically connected to the electronic element, allowing for reduced thickness and improved structural rigidity, and a method involving a carrier with recesses and wet etching to fabricate the package.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a silicon interposer is used to overcome CTE mismatch between semiconductor chip and packaging substrate, then reliability of electrical connection is improved, but fabrication cost increases significantly
Solution Approach 1:
The patent extracts and eliminates the silicon interposer from the packaging structure, replacing it with a substrate that has an insulating layer and circuit layer integrated directly onto it. This removal of the interposer resolves the high fabrication cost issue while maintaining the necessary electrical connection reliability through alternative design approaches.
Solution Approach 2:
The patent replaces the expensive silicon interposer with a more cost-effective substrate structure that integrates the insulating and circuit layers directly. This substitution uses cheaper materials and processes while achieving the same functional outcome of providing electrical connections between the chip and packaging substrate.
2Reliability
If a silicon interposer is used to reduce CTE mismatch, then reliability is improved, but manufacturing complexity and difficulty increase
Solution Approach 1:
The patent merges the insulating layer and circuit layer into a single integrated structure that is formed directly on the substrate. This consolidation eliminates the need for separate silicon interposer fabrication and assembly steps, reducing manufacturing complexity while maintaining electrical connection reliability through the integrated design.
3Ease of manufacture
If conventional packaging without interposer is used, then fabrication cost is reduced, but CTE mismatch causes delamination and warpage
Solution Approach 1:
The patent introduces an insulating layer as an intermediary between the substrate and the circuit elements. This insulating layer acts as a mediator that accommodates CTE differences while providing a stable foundation for the circuit layer, preventing delamination and warpage without requiring a silicon interposer.
4Reliability
If silicon interposer with TSVs is used, then electrical connection reliability is improved, but fabrication yield decreases
Solution Approach 1:
The patent removes the TSV fabrication process entirely by eliminating the silicon interposer. Instead, electrical connections are achieved through conductive patterns formed directly on the substrate, which uses simpler, more reliable manufacturing processes that do not involve complex through-silicon via formation and filling operations.
Data Source
AI summary
A semiconductor package is provided, including: an insulating base body having a first surface with an opening and a second surface opposite to the first surface; an insulating extending body extending outward from an edge of the first surface of the insulating base body, wherein the insulating extending body is less in thickness than the insulating base body; an electronic element having opposite active and inactive surfaces and disposed in the opening with its inactive surface facing the insulating base body; a dielectric layer formed in the opening of the insulating base body and on the first surface of the insulating base body, the insulating extending body and the active surface of the electronic element; and a circuit layer formed on the dielectric layer and electrically connected to the electronic element. The configuration of the insulating layer of the invention facilitates to enhance the overall structural rigidity of the package.