Semiconductor Package Structure Eliminating Thinning Steps
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Solution Overview
Problem
The complexity of semiconductor package manufacturing increases as package dimensions decrease, making it challenging to miniaturize while maintaining process simplicity and reducing costs.
Innovation Solution
A package structure and manufacturing method involving a carrier with a semiconductor chip, an insulating material layer, conductive posts and vias, and a redistribution layer, where the insulating material layer is patterned to form openings, allowing for the omission of thinning steps and simplification of the manufacturing process, thereby reducing material costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional thinning steps are performed to planarize surfaces of conductive vias, semiconductor chip and insulating encapsulant, then manufacturing precision is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The insulating material layer is designed with sufficient thickness from the beginning to accommodate all subsequent conductive structures (conductive posts and conductive vias) without requiring thinning operations. This preliminary design decision eliminates the need for complex thinning and planarization steps while maintaining the required manufacturing precision.
Solution Approach 2:
The patent extracts and eliminates the thinning steps from the conventional manufacturing process. By designing the insulating material layer to be sufficiently thick from the outset, the harmful thinning operations are removed entirely, simplifying the manufacturing process while maintaining precision requirements.
2Ease of manufacture
If the insulating material layer thickness is increased to be greater than the semiconductor chip thickness, then the need for thinning steps is eliminated, but the volume of the package increases
Solution Approach 1:
The patent redistributes the thickness allocation in the vertical dimension. By increasing the insulating material layer thickness and correspondingly adjusting other layer thicknesses (semiconductor chip, conductive posts, conductive vias), the total package volume is maintained while achieving manufacturing simplicity.
Solution Approach 2:
The patent changes the thickness parameter of the insulating material layer from being less than or equal to the chip thickness to being greater than the chip thickness. This parameter change enables the elimination of thinning steps while the overall package volume is controlled through coordinated adjustment of other dimensional parameters.
3Reliability
If multiple thinning and planarization steps are performed, then the surfaces are properly prepared for subsequent processing, but the manufacturing time and cost increase
Solution Approach 1:
The insulating material layer is prepared with appropriate thickness and surface characteristics in advance, before any conductive structures are formed. This preliminary preparation ensures that subsequent processing steps can proceed directly without requiring intermediate thinning or planarization operations, thereby maintaining surface preparation quality while reducing manufacturing cycle time.
Data Source
AI summary
A manufacturing method of a package structure is provided. The method includes the following steps. A semiconductor chip is bonded on a carrier, wherein the semiconductor chip comprises a plurality of conductive pads. An insulating material layer is formed over the carrier and encapsulating the semiconductor chip, wherein a thickness of the insulating material layer is greater than a thickness of the semiconductor chip. A first surface of the insulating material layer is patterned to form first openings that expose the conductive pads of the semiconductor chip, and second openings that penetrate through the insulating material layer. A plurality of conductive posts is formed in the first openings, wherein the plurality of conductive posts is electrically connected to the plurality of conductive pads of the semiconductor chip. A plurality of conductive vias is formed in the second opening.