Semiconductor Package Insulating Spacers for Void-Free Mounting

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Solution Overview

Problem

During the mounting of semiconductor elements on a package substrate, insufficient spacing can lead to voids in the molding member and the presence of foreign substances, causing potential short circuits due to inadequate distance between the semiconductor elements and the substrate.

Innovation Solution

The implementation of insulating structures with a stepping stone configuration on the package substrate, comprising a lower and upper insulator, to increase the spacing between the semiconductor elements and the substrate, thereby preventing voids and foreign substances from forming.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the spacing distance between semiconductor elements and package substrate is reduced, then mounting density is improved, but voids occur in molding member and foreign substances remain causing short circuiting

Engineering Contradiction:
Improvemounting densityVSAvoidshort circuit prevention
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

An insulating structure is introduced as an intermediary component between the semiconductor element and the package substrate. This mediator maintains electrical isolation and prevents short circuits while enabling closer spacing, thus resolving the contradiction between mounting density and reliability.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The insulating structure extends in the vertical dimension (thickness direction) to provide sufficient spacing distance. By utilizing the vertical dimension rather than increasing horizontal spacing, the patent achieves both high mounting density and reliable electrical isolation.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If insulating structures are added to increase spacing, then reliability is improved by preventing voids and foreign substances, but device complexity increases

Engineering Contradiction:
Improvevoid preventionVSAvoidstructure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The insulating structure is merged with the existing substrate structure by forming it on the substrate surface using the same or similar materials and processes. This integration approach adds the necessary insulation function without significantly increasing overall device complexity.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The insulating structure is formed in advance during the substrate fabrication process, before semiconductor element mounting. This preliminary action ensures the spacing structure is already in place, simplifying subsequent assembly steps and reducing overall manufacturing complexity.

Inventive Principle:
Principle #10Preliminary action

3Manufacturing precision

If insulating structures are formed with multiple layers, then spacing precision is improved, but manufacturing time increases

Engineering Contradiction:
Improvespacing precisionVSAvoidmanufacturing time
Core Design Contradiction:
Manufacturing precisionVSLoss of time

Solution Approach 1:

Multiple insulating layers are formed by repeating the same deposition and patterning processes, merging the fabrication steps into a standardized sequence. This approach achieves precise spacing control while maintaining manufacturing efficiency through process repetition rather than developing entirely new multi-step procedures.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS20240429151A1Semiconductor package and method of manufacturing semiconductor package
Publication Date: 2024.12.26 SAMSUNG ELECTRONICS CO LTD
  • US20240429151A1 patent drawing
  • US20240429151A1 patent drawing
  • US20240429151A1 patent drawing

AI summary

A semiconductor package includes a package substrate having a first surface and a second surface opposite to each other, the package substrate comprising a plurality of first substrate pads and a plurality of second substrate pads that are exposed from the first surface; a semiconductor device mounted on the first surface of the package substrate; at least one semiconductor element on the package substrate, the at least one semiconductor element spaced apart from the semiconductor device, the at least one semiconductor element being mounted on the package substrate via solder members that are disposed on the plurality of second substrate pads; and a plurality of insulating structures on the first surface of the package substrate to space a lower surface of the at least one semiconductor element from the first surface of the package substrate.