Semiconductor Package Insulation Layer for High-Voltage Breakdown
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Solution Overview
Problem
Current chip embedding processes are inadequate for high voltage applications beyond 650 V due to unsuitable breakdown voltage, ion impurity levels, and lack of pre-test capability for insulation properties in semiconductor packages.
Innovation Solution
A semiconductor package design featuring a die carrier with a semiconductor die, electrical connectors, an encapsulant, and an insulation layer on the die carrier's second main face, allowing for improved insulation and thermal management, and a method for fabricating the package that includes applying an insulation layer using materials like organic or ceramic insulators, enabling testing of insulation properties before final assembly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If current PCB materials are used for chip embedding, then the manufacturing process is simple and cost-effective, but the breakdown voltage and ion impurity level are insufficient for high voltage applications above 650 V
Solution Approach 1:
The patent applies composite materials by combining organic insulator materials (epoxy resin, polyimide) with ceramic particles (alumina, silica) to create an insulation layer that achieves both high breakdown voltage for 1700V applications and manufacturing feasibility. This composite approach resolves the contradiction by providing the necessary electrical insulation properties while maintaining compatibility with existing PCB embedding processes.
2Reliability
If current chip embedding process is used, then the process is straightforward, but pre-test capability for insulation properties is missing
Solution Approach 1:
The patent implements preliminary action by incorporating an dedicated insulation layer between the PCB and encapsulant that can be tested for insulation properties before final assembly. This allows pre-testing of insulation characteristics at the package level rather than only at the finished product level, enabling early detection of insulation deficiencies without significantly complicating the overall manufacturing process.
3Reliability
If insulation layer is added to die carrier, then insulation reliability for high voltage is improved, but manufacturing process complexity increases
Solution Approach 1:
The patent applies merging by integrating the insulation layer formation into the existing encapsulant application process. The insulation layer is applied to the die carrier before die attachment, and the encapsulant is then applied over both the die and insulation layer in a single encapsulation step. This combines multiple functions (insulation provision and structural encapsulation) into unified process steps, minimizing additional manufacturing complexity while ensuring insulation reliability.
Data Source
AI summary
A semiconductor package includes: a die carrier having a first main face and a second main face opposite to the first main face; a semiconductor die disposed on the die carrier, the semiconductor die including a first pad and a second pad; a first electrical connector disposed on the first pad; an encapsulant at least partially covering the semiconductor die, the die carrier, and the first electrical connector; and an insulation layer disposed on the second main face of the die carrier.