Semiconductor Package Layout for Higher Insulation Withstand Voltage
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Solution Overview
Problem
Semiconductor devices with multiple elements in a single package face challenges in maintaining insulation withstand voltage due to differences in power supply voltages between conduction paths, leading to potential electrical insulation failures.
Innovation Solution
A semiconductor device design featuring conductive support members with distinct die pads and insulating elements, along with a sealing resin, that creates a structured configuration to enhance insulation between circuits, including specific geometries and surface features on the die pads and terminals to manage electrical field distribution effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple semiconductor elements are mounted in one package with different power supply voltages, then integration density is improved, but insulation withstand voltage between conduction paths deteriorates
Solution Approach 1:
The die pad structure transitions from a conventional planar layout to a three-dimensional configuration where the second die pad is positioned at a height different from the first die pad in the thickness direction. This vertical separation creates additional insulation distance between conduction paths with different power supply voltages, thereby improving insulation withstand voltage while maintaining high integration density within the package.
Solution Approach 2:
The conductive support member is segmented into multiple die pads (first die pad and second die pad) that are spatially separated and electrically isolated from each other. Each die pad serves a specific function with its own power supply voltage, and the segmentation allows independent voltage management while maintaining overall package integration.
2Area of stationary object
If die pads are positioned close together to reduce package size, then package compactness is improved, but electric field strength between die pads increases
Solution Approach 1:
Instead of increasing horizontal separation distance between die pads, the invention utilizes the thickness direction (vertical dimension) to create separation. The second die pad is positioned at a different height than the first die pad, which reduces the electric field strength between them without increasing the package footprint area, thus maintaining compactness while managing electric field stress.
3Reliability
If insulation distance between die pads is increased to improve insulation withstand voltage, then insulation reliability is improved, but package area increases
Solution Approach 1:
The insulation distance is extended in the thickness direction rather than in the planar area. By positioning the second die pad at a different height from the first die pad, the invention achieves greater insulation withstand voltage through increased vertical separation distance without expanding the package footprint, thus resolving the contradiction between insulation reliability and package area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution significantly improves insulation withstand voltage by reducing electric field strength and enhancing dielectric strength between circuits, thereby ensuring reliable operation under varying power supply conditions.
Implementation Method 1
a sealing resin that covers the first die pad, the second die pad, the first semiconductor element, the second semiconductor element, and the insulating element and insulates the first die pad and the second die pad from each other
Implementation Method 2
an insulating element that conducts to the first semiconductor element and the second semiconductor element and insulates the first circuit and the second circuit from each other
Data Source
AI summary
A semiconductor device includes a first die pad, a second die pad, a first semiconductor element, a second semiconductor element, an insulating element, first terminals, second terminals, and a sealing resin. The sealing resin has a first side surface located on one side of a first direction, a second side surface located on the other side of the first direction, and third and fourth side surfaces that are separated from each other in a second direction orthogonal to both a thickness direction and the first direction and are connected to the first and second side surfaces. A first gate mark having a surface roughness larger than the other regions of the third side surface is formed on the third side surface. When viewed along the second direction, the first gate mark overlaps a pad gap provided between the first die pad and the second die pad in the first direction.