Semiconductor Package Interconnection Member Eliminates RDL
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Solution Overview
Problem
The miniaturization of semiconductor devices has increased manufacturing complexity, leading to challenges such as poor electrical interconnection and higher costs, particularly in the chip-on-chip technique where conventional Redistribution Layer (RDL) layers complicate the structure and manufacturing process.
Innovation Solution
A semiconductor package design that eliminates the conventional RDL layer by using an interconnection member with connection plates and bumps to couple two stacked dies, along with bonding wires to connect the dies to a package substrate, simplifying the manufacturing process and reducing complexity and costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional RDL layers are used to connect two stacked chips, then electrical interconnection is achieved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent removes the conventional RDL (Redistribution Layer) structure from the chip stack. Instead of using traditional RDL layers to achieve electrical interconnection between stacked chips, the invention extracts this function and replaces it with direct bonding wire connections and simplified connection plates, thereby reducing manufacturing complexity while maintaining electrical connectivity
Solution Approach 2:
The patent combines multiple functions into fewer components. The connection plate serves both as a mechanical support structure and as an electrical connection interface, eliminating the need for separate RDL layers. This merging of structural and electrical functions reduces the overall device complexity
2Reliability
If conventional RDL layers are used to connect two stacked chips, then electrical interconnection is achieved, but manufacturing cost increases
Solution Approach 1:
By extracting and removing the RDL layer from the manufacturing process, the patent eliminates the complex and costly steps associated with RDL deposition, patterning, and alignment. The simplified structure using connection plates and bonding wires reduces material costs and manufacturing overhead
Solution Approach 2:
The patent employs bonding wires as a cost-effective alternative to expensive RDL layers. Bonding wires are inexpensive, easy to manufacture, and can be rapidly deposited using established wire bonding technology, making them an economical choice for achieving electrical interconnection
3Adaptability or versatility
If chip-on-chip technique is used for miniaturized semiconductor devices, then device functionality increases, but manufacturing complexity increases
Solution Approach 1:
The patent segments the interconnection function into distinct, simple components: connection plates attached to each chip and bonding wires connecting these plates. This segmentation avoids the need for complex integrated RDL structures, making the manufacturing process more manageable while still achieving the desired chip-on-chip functionality
Solution Approach 2:
The connection plate acts as an intermediary element between the stacked chips and the bonding wires. This mediator simplifies the interface requirements, allowing for easier alignment and connection without the need for complex RDL patterns, thus reducing manufacturing complexity while maintaining device functionality
Data Source
AI summary
A semiconductor package is provided which includes a package substrate, a first die, a second die, an interconnection member and a number of bonding wires. The first die is disposed on the package substrate. The second die is disposed over the first die. The interconnection member is configured for coupling the first die and the second die and comprises a first connection plate, a second connection plate and a bump. The first connection plate is connected to the first die. The second connection plate is connected to the second die. The bump couples the first connection plate and the second connection plate. The bonding wires couple the interconnection member to the package substrate, the first die and the second die.