Semiconductor Package Interconnection Patterning for Compact Design
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Solution Overview
Problem
Conventional semiconductor packages are inefficient in reducing package size, leading to excess cost and decreased reliability due to constraints in minimizing the pitch between interconnection structures and adjusting the thickness of the molded part.
Innovation Solution
A method of manufacturing semiconductor packages by patterning interconnection structures in smaller sizes to reduce the distance between them and adjusting the thickness of the molded part through the use of temporary structures, which are later removed to form conductive bumps or solder bumps, allowing for a more compact package design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If conventional packaging methods are used, then manufacturing process is simpler, but package size cannot be reduced effectively
Solution Approach 1:
The patent applies preliminary action by forming a mandrel pattern before molding the packaged device. The mandrel structures are created in advance on the semiconductor substrate, defining the future interconnection structure locations. This preliminary patterning enables subsequent molding processes to accurately form interconnections at reduced pitch without requiring complex real-time alignment systems, thus reducing package size while managing manufacturing complexity.
Solution Approach 2:
The patent uses mandrels as intermediary structures that facilitate the formation of interconnections. These temporary mandrel structures serve as mediators between the molding process and the final interconnection geometry. The mandrels are formed first, then molding compound is applied around them, and finally the mandrels are removed to leave precisely formed interconnection structures with minimized pitch, achieving compact packaging without excessive process complexity.
2Volume of moving object
If pitch between interconnection structures is minimized, then package size is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies copying by using mandrel structures as physical templates or copies of the desired interconnection pattern. The mandrels are formed with the target pitch and geometry, then the molding process replicates this pattern by forming interconnections around the mandrels. This copying approach transfers the precision requirement from the difficult molding alignment step to the more controllable mandrel formation step, enabling minimized pitch while managing manufacturing precision requirements.
Solution Approach 2:
The patent performs preliminary patterning to create mandrels with the minimized pitch before the molding process. By establishing the precise pitch geometry in advance through mandrel formation (which can use standard photolithography and etching processes), the subsequent molding step only needs to replicate this pre-established pattern, significantly reducing the precision burden on the molding process and enabling compact interconnection spacing.
3Volume of moving object
If molded part thickness is adjusted for compact design, then package size is reduced, but process control becomes more difficult
Solution Approach 1:
The patent uses mandrels as intermediary structures that define and control the thickness of the molded part. The mandrels are positioned at specific heights on the semiconductor substrate, and the molding compound is applied to a controlled thickness above these mandrels. This mandrel-based approach acts as a physical stop or reference that simplifies thickness control during molding, enabling compact package design with reduced molded part thickness while maintaining ease of manufacture through straightforward process control.
Data Source
AI summary
A semiconductor device and a manufacturing method thereof, which can reduce a size of the semiconductor device. As a non-limiting example, various aspects of this disclosure provide for a reduction in package size based at least in part on patterning techniques for forming interconnection structures.